soc: esp32: Update soc startup and cache init
Updated the cache init functions and clean-up the soc startup function. Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit is contained in:
Marek Matej
Carles Cufí
parent
548e8b717d
commit
02d157b8db
2 changed files with 64 additions and 122 deletions
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@ -40,16 +40,29 @@
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#include <zephyr/sys/printk.h>
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extern void z_cstart(void);
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extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways,
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uint8_t cfg_cache_line_size);
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extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways,
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uint8_t cfg_cache_line_size);
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extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
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extern void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num,
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uint32_t rodata_start, uint32_t rodata_end, int i_off,
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int ro_off);
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extern int _rodata_reserved_start;
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extern int _rodata_reserved_end;
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#ifndef CONFIG_MCUBOOT
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/*
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* This function is a container for SoC patches
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* that needs to be applied during the startup.
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*/
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static void IRAM_ATTR esp_errata(void)
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{
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/* Handle the clock gating fix */
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REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
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/* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETTING
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* signals to ensure that the App core stops running in single-core mode.
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*/
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REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
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REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
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/* Handle the Dcache case following the IDF startup code */
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#if CONFIG_ESP32S3_DATA_CACHE_16KB
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Cache_Invalidate_DCache_All();
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Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000);
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#endif
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}
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#endif /* CONFIG_MCUBOOT */
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/*
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* This is written in C rather than assembly since, during the port bring up,
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@ -58,7 +71,6 @@ extern int _rodata_reserved_end;
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*/
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void IRAM_ATTR __esp_platform_start(void)
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{
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volatile soc_reset_reason_t rst_reas[SOC_CPU_CORES_NUM];
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extern uint32_t _init_start;
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/* Move the exception vector table to IRAM. */
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@ -82,39 +94,15 @@ void IRAM_ATTR __esp_platform_start(void)
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}
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#else
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/* Configure the mode of instruction cache : cache size, cache line size. */
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rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE,
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CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS,
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CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE);
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esp_config_instruction_cache_mode();
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/* If we need use SPIRAM, we should use data cache.
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* Configure the mode of data : cache size, cache line size.
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*/
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Cache_Suspend_DCache();
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rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE,
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CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS,
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CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
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Cache_Resume_DCache(0);
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/* Configure the Cache MMU size for instruction and rodata in flash. */
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uint32_t rodata_reserved_start_align =
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(uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
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uint32_t cache_mmu_irom_size =
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((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t);
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uint32_t cache_mmu_drom_size =
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(((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align + MMU_PAGE_SIZE - 1)
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/ MMU_PAGE_SIZE) * sizeof(uint32_t);
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Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
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esp_config_data_cache_mode();
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REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
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/* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETTING
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* signals to ensure that the App core stops running in single-core mode.
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*/
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REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
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REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
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#if CONFIG_ESP32S3_DATA_CACHE_16KB
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Cache_Invalidate_DCache_All();
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Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000);
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#endif
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/* Apply SoC patches */
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esp_errata();
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/* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check on startup sequence
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* related issues in application. Hence disable that as we are about to start
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@ -6,99 +6,53 @@
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#include "soc.h"
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/*
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* Instruction Cache definitions
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*/
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#if defined(CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB)
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#define ESP32S3_ICACHE_SIZE ICACHE_SIZE_16KB
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#else
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#define ESP32S3_ICACHE_SIZE ICACHE_SIZE_32KB
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#endif
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#if defined(CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B)
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#define ESP32S3_ICACHE_LINE_SIZE CACHE_LINE_SIZE_16B
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#else
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#define ESP32S3_ICACHE_LINE_SIZE CACHE_LINE_SIZE_32B
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#endif
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/*
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* Data Cache definitions
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*/
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#if defined(CONFIG_ESP32S3_DATA_CACHE_16KB) || defined(CONFIG_ESP32S3_DATA_CACHE_32KB)
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#define ESP32S3_DCACHE_SIZE DCACHE_SIZE_32KB
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#else
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#define ESP32S3_DCACHE_SIZE DCACHE_SIZE_64KB
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#endif
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#if defined(CONFIG_ESP32S3_DATA_CACHE_LINE_16B)
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#define ESP32S3_DCACHE_LINE_SIZE CACHE_LINE_SIZE_16B
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#elif defined(CONFIG_ESP32S3_DATA_CACHE_LINE_32B)
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#define ESP32S3_DCACHE_LINE_SIZE CACHE_LINE_SIZE_32B
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#else
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#define ESP32S3_DCACHE_LINE_SIZE CACHE_LINE_SIZE_32B
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#endif
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#define CACHE_MEMORY_ICACHE_LOW CACHE_ICACHE0
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#ifndef CONFIG_MCUBOOT
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extern int _rodata_reserved_start;
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extern int _rodata_reserved_end;
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extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways,
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uint8_t cfg_cache_line_size);
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extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways,
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uint8_t cfg_cache_line_size);
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extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
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extern void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num,
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uint32_t rodata_start, uint32_t rodata_end,
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int i_off, int ro_off);
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extern void Cache_Enable_ICache(uint32_t autoload);
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void IRAM_ATTR esp_config_instruction_cache_mode(void)
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{
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cache_size_t cache_size;
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cache_ways_t cache_ways;
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cache_line_size_t cache_line_size;
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rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE,
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CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS,
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CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE);
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#if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB
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Cache_Occupy_ICache_MEMORY(CACHE_MEMORY_IBANK0, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_HALF;
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#else
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Cache_Occupy_ICache_MEMORY(CACHE_MEMORY_IBANK0, CACHE_MEMORY_IBANK1);
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cache_size = CACHE_SIZE_FULL;
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#endif
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#if CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS
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cache_ways = CACHE_4WAYS_ASSOC;
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#else
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cache_ways = CACHE_8WAYS_ASSOC;
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#endif
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#if CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B
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cache_line_size = CACHE_LINE_SIZE_16B;
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#elif CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B
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cache_line_size = CACHE_LINE_SIZE_32B;
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#else
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cache_line_size = CACHE_LINE_SIZE_64B;
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#endif
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Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);
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Cache_Invalidate_ICache_All();
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Cache_Enable_ICache(0);
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Cache_Suspend_DCache();
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}
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void IRAM_ATTR esp_config_data_cache_mode(void)
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{
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cache_size_t cache_size;
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cache_ways_t cache_ways;
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cache_line_size_t cache_line_size;
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int s_instr_flash2spiram_off = 0;
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int s_rodata_flash2spiram_off = 0;
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#if CONFIG_ESP32S3_DATA_CACHE_32KB
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Cache_Occupy_DCache_MEMORY(CACHE_MEMORY_DBANK1, CACHE_MEMORY_INVALID);
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cache_size = CACHE_SIZE_HALF;
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#else
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Cache_Occupy_DCache_MEMORY(CACHE_MEMORY_DBANK0, CACHE_MEMORY_DBANK1);
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cache_size = CACHE_SIZE_FULL;
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#endif
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#if CONFIG_ESP32S3_DATA_CACHE_4WAYS
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cache_ways = CACHE_4WAYS_ASSOC;
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#else
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cache_ways = CACHE_8WAYS_ASSOC;
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#endif
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#if CONFIG_ESP32S3_DATA_CACHE_LINE_16B
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cache_line_size = CACHE_LINE_SIZE_16B;
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#elif CONFIG_ESP32S3_DATA_CACHE_LINE_32B
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cache_line_size = CACHE_LINE_SIZE_32B;
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#else
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cache_line_size = CACHE_LINE_SIZE_64B;
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#endif
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Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
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Cache_Invalidate_DCache_All();
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rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE,
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CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS,
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CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
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Cache_Resume_DCache(0);
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/* Configure the Cache MMU size for instruction and rodata in flash. */
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uint32_t rodata_reserved_start_align =
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(uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
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uint32_t cache_mmu_irom_size =
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((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t);
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uint32_t cache_mmu_drom_size =
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(((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align + MMU_PAGE_SIZE - 1)
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/ MMU_PAGE_SIZE) * sizeof(uint32_t);
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Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
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Cache_Set_IDROM_MMU_Info(cache_mmu_irom_size / sizeof(uint32_t),
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cache_mmu_drom_size / sizeof(uint32_t),
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(uint32_t)&_rodata_reserved_start,
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(uint32_t)&_rodata_reserved_end,
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s_instr_flash2spiram_off,
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s_rodata_flash2spiram_off);
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}
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#endif /* CONFIG_MCUBOOT */
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