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soc: esp32: Update soc startup and cache init

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Updated the cache init functions
and clean-up the soc startup function.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit is contained in:
Marek Matej 2023-05-29 20:42:14 +02:00 • committed by Carles Cufí
commit 02d157b8db
2 changed files with 64 additions and 122 deletions
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66
soc/xtensa/esp32s3/soc.c
View file

@ -40,16 +40,29 @@
#include <zephyr/sys/printk.h> #include <zephyr/sys/printk.h>
extern void z_cstart(void); extern void z_cstart(void);
extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways,
uint8_t cfg_cache_line_size); #ifndef CONFIG_MCUBOOT
extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, /*
uint8_t cfg_cache_line_size); * This function is a container for SoC patches
extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); * that needs to be applied during the startup.
extern void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num, */
uint32_t rodata_start, uint32_t rodata_end, int i_off, static void IRAM_ATTR esp_errata(void)
int ro_off); {
extern int _rodata_reserved_start; /* Handle the clock gating fix */
extern int _rodata_reserved_end; REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
/* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETTING
* signals to ensure that the App core stops running in single-core mode.
*/
REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
/* Handle the Dcache case following the IDF startup code */
#if CONFIG_ESP32S3_DATA_CACHE_16KB
Cache_Invalidate_DCache_All();
Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000);
#endif
}
#endif /* CONFIG_MCUBOOT */
/* /*
* This is written in C rather than assembly since, during the port bring up, * This is written in C rather than assembly since, during the port bring up,
@ -58,7 +71,6 @@ extern int _rodata_reserved_end;
*/ */
void IRAM_ATTR __esp_platform_start(void) void IRAM_ATTR __esp_platform_start(void)
{ {
volatile soc_reset_reason_t rst_reas[SOC_CPU_CORES_NUM];
extern uint32_t _init_start; extern uint32_t _init_start;
/* Move the exception vector table to IRAM. */ /* Move the exception vector table to IRAM. */
@ -82,39 +94,15 @@ void IRAM_ATTR __esp_platform_start(void)
} }
#else #else
/* Configure the mode of instruction cache : cache size, cache line size. */ /* Configure the mode of instruction cache : cache size, cache line size. */
rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE, esp_config_instruction_cache_mode();
CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS,
CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE);
/* If we need use SPIRAM, we should use data cache. /* If we need use SPIRAM, we should use data cache.
* Configure the mode of data : cache size, cache line size. * Configure the mode of data : cache size, cache line size.
*/ */
Cache_Suspend_DCache(); esp_config_data_cache_mode();
rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE,
CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS,
CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
Cache_Resume_DCache(0);
/* Configure the Cache MMU size for instruction and rodata in flash. */
uint32_t rodata_reserved_start_align =
(uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
uint32_t cache_mmu_irom_size =
((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t);
uint32_t cache_mmu_drom_size =
(((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align + MMU_PAGE_SIZE - 1)
/ MMU_PAGE_SIZE) * sizeof(uint32_t);
Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN); /* Apply SoC patches */
/* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETTING esp_errata();
* signals to ensure that the App core stops running in single-core mode.
*/
REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING);
#if CONFIG_ESP32S3_DATA_CACHE_16KB
Cache_Invalidate_DCache_All();
Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000);
#endif
/* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check on startup sequence /* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check on startup sequence
* related issues in application. Hence disable that as we are about to start * related issues in application. Hence disable that as we are about to start

120
soc/xtensa/esp32s3/soc_cache.c
View file

@ -6,99 +6,53 @@
#include "soc.h" #include "soc.h"
/*
* Instruction Cache definitions
*/
#if defined(CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB)
#define ESP32S3_ICACHE_SIZE ICACHE_SIZE_16KB
#else
#define ESP32S3_ICACHE_SIZE ICACHE_SIZE_32KB
#endif
#if defined(CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B)
#define ESP32S3_ICACHE_LINE_SIZE CACHE_LINE_SIZE_16B
#else
#define ESP32S3_ICACHE_LINE_SIZE CACHE_LINE_SIZE_32B
#endif
/*
* Data Cache definitions
*/
#if defined(CONFIG_ESP32S3_DATA_CACHE_16KB) || defined(CONFIG_ESP32S3_DATA_CACHE_32KB)
#define ESP32S3_DCACHE_SIZE DCACHE_SIZE_32KB
#else
#define ESP32S3_DCACHE_SIZE DCACHE_SIZE_64KB
#endif
#if defined(CONFIG_ESP32S3_DATA_CACHE_LINE_16B)
#define ESP32S3_DCACHE_LINE_SIZE CACHE_LINE_SIZE_16B
#elif defined(CONFIG_ESP32S3_DATA_CACHE_LINE_32B)
#define ESP32S3_DCACHE_LINE_SIZE CACHE_LINE_SIZE_32B
#else
#define ESP32S3_DCACHE_LINE_SIZE CACHE_LINE_SIZE_32B
#endif
#define CACHE_MEMORY_ICACHE_LOW CACHE_ICACHE0
#ifndef CONFIG_MCUBOOT #ifndef CONFIG_MCUBOOT
extern int _rodata_reserved_start;
extern int _rodata_reserved_end;
extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways,
uint8_t cfg_cache_line_size);
extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways,
uint8_t cfg_cache_line_size);
extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
extern void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num,
uint32_t rodata_start, uint32_t rodata_end,
int i_off, int ro_off);
extern void Cache_Enable_ICache(uint32_t autoload); extern void Cache_Enable_ICache(uint32_t autoload);
void IRAM_ATTR esp_config_instruction_cache_mode(void) void IRAM_ATTR esp_config_instruction_cache_mode(void)
{ {
cache_size_t cache_size; rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE,
cache_ways_t cache_ways; CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS,
cache_line_size_t cache_line_size; CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE);
#if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB Cache_Suspend_DCache();
Cache_Occupy_ICache_MEMORY(CACHE_MEMORY_IBANK0, CACHE_MEMORY_INVALID);
cache_size = CACHE_SIZE_HALF;
#else
Cache_Occupy_ICache_MEMORY(CACHE_MEMORY_IBANK0, CACHE_MEMORY_IBANK1);
cache_size = CACHE_SIZE_FULL;
#endif
#if CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS
cache_ways = CACHE_4WAYS_ASSOC;
#else
cache_ways = CACHE_8WAYS_ASSOC;
#endif
#if CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B
cache_line_size = CACHE_LINE_SIZE_16B;
#elif CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B
cache_line_size = CACHE_LINE_SIZE_32B;
#else
cache_line_size = CACHE_LINE_SIZE_64B;
#endif
Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);
Cache_Invalidate_ICache_All();
Cache_Enable_ICache(0);
} }
void IRAM_ATTR esp_config_data_cache_mode(void) void IRAM_ATTR esp_config_data_cache_mode(void)
{ {
cache_size_t cache_size; int s_instr_flash2spiram_off = 0;
cache_ways_t cache_ways; int s_rodata_flash2spiram_off = 0;
cache_line_size_t cache_line_size;
#if CONFIG_ESP32S3_DATA_CACHE_32KB rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE,
Cache_Occupy_DCache_MEMORY(CACHE_MEMORY_DBANK1, CACHE_MEMORY_INVALID); CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS,
cache_size = CACHE_SIZE_HALF; CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
#else Cache_Resume_DCache(0);
Cache_Occupy_DCache_MEMORY(CACHE_MEMORY_DBANK0, CACHE_MEMORY_DBANK1);
cache_size = CACHE_SIZE_FULL; /* Configure the Cache MMU size for instruction and rodata in flash. */
#endif uint32_t rodata_reserved_start_align =
#if CONFIG_ESP32S3_DATA_CACHE_4WAYS (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
cache_ways = CACHE_4WAYS_ASSOC; uint32_t cache_mmu_irom_size =
#else ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t);
cache_ways = CACHE_8WAYS_ASSOC; uint32_t cache_mmu_drom_size =
#endif (((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align + MMU_PAGE_SIZE - 1)
#if CONFIG_ESP32S3_DATA_CACHE_LINE_16B / MMU_PAGE_SIZE) * sizeof(uint32_t);
cache_line_size = CACHE_LINE_SIZE_16B; Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
#elif CONFIG_ESP32S3_DATA_CACHE_LINE_32B
cache_line_size = CACHE_LINE_SIZE_32B; Cache_Set_IDROM_MMU_Info(cache_mmu_irom_size / sizeof(uint32_t),
#else cache_mmu_drom_size / sizeof(uint32_t),
cache_line_size = CACHE_LINE_SIZE_64B; (uint32_t)&_rodata_reserved_start,
#endif (uint32_t)&_rodata_reserved_end,
Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size); s_instr_flash2spiram_off,
Cache_Invalidate_DCache_All(); s_rodata_flash2spiram_off);
} }
#endif /* CONFIG_MCUBOOT */ #endif /* CONFIG_MCUBOOT */