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drivers/gpio: stm32: Change order of registers configuration

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During implementation of i2c pinctrl configuration within i2c driver,
it appears that current order of register configuration used to
generate a spike on I2C bus, leading to broken configuration with
I2C device.
Reverse the order so that pin mode setting is done only after pupd,
speed and type are set, in order to avoid generating unwanted
artefacts on the bus.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2020-10-08 15:58:20 +02:00 • committed by Carles Cufí
commit 02bd657ce3
1 changed files with 20 additions and 19 deletions
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39
drivers/gpio/gpio_stm32.c
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@ -126,8 +126,6 @@ int gpio_stm32_configure(uint32_t *base_addr, int pin, int conf, int altf)
} else if (temp == STM32_CNF_IN_FLOAT) {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_FLOATING);
} else {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_INPUT);
temp = conf & (STM32_PUPD_MASK << STM32_PUPD_SHIFT);
if (temp == STM32_PUPD_PULL_UP) {
@ -135,17 +133,11 @@ int gpio_stm32_configure(uint32_t *base_addr, int pin, int conf, int altf)
} else {
LL_GPIO_SetPinPull(gpio, pin_ll, LL_GPIO_PULL_DOWN);
}
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_INPUT);
}
} else {
temp = conf & (STM32_CNF_OUT_1_MASK << STM32_CNF_OUT_1_SHIFT);
if (temp == STM32_CNF_GP_OUTPUT) {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_OUTPUT);
} else {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_ALTERNATE);
}
temp = conf & (STM32_CNF_OUT_0_MASK << STM32_CNF_OUT_0_SHIFT);
if (temp == STM32_CNF_PUSH_PULL) {
@ -163,6 +155,14 @@ int gpio_stm32_configure(uint32_t *base_addr, int pin, int conf, int altf)
} else {
LL_GPIO_SetPinSpeed(gpio, pin_ll, LL_GPIO_SPEED_FREQ_HIGH);
}
temp = conf & (STM32_CNF_OUT_1_MASK << STM32_CNF_OUT_1_SHIFT);
if (temp == STM32_CNF_GP_OUTPUT) {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_OUTPUT);
} else {
LL_GPIO_SetPinMode(gpio, pin_ll, LL_GPIO_MODE_ALTERNATE);
}
}
#else
unsigned int mode, otype, ospeed, pupd;
@ -173,15 +173,6 @@ int gpio_stm32_configure(uint32_t *base_addr, int pin, int conf, int altf)
pupd = conf & (STM32_PUPDR_MASK << STM32_PUPDR_SHIFT);
z_stm32_hsem_lock(CFG_HW_GPIO_SEMID, HSEM_LOCK_DEFAULT_RETRY);
LL_GPIO_SetPinMode(gpio, pin_ll, mode >> STM32_MODER_SHIFT);
if (STM32_MODER_ALT_MODE == mode) {
if (pin < 8) {
LL_GPIO_SetAFPin_0_7(gpio, pin_ll, altf);
} else {
LL_GPIO_SetAFPin_8_15(gpio, pin_ll, altf);
}
}
#if defined(CONFIG_SOC_SERIES_STM32L4X) && defined(GPIO_ASCR_ASC0)
/*
@ -199,6 +190,16 @@ int gpio_stm32_configure(uint32_t *base_addr, int pin, int conf, int altf)
LL_GPIO_SetPinPull(gpio, pin_ll, pupd >> STM32_PUPDR_SHIFT);
if (mode == STM32_MODER_ALT_MODE) {
if (pin < 8) {
LL_GPIO_SetAFPin_0_7(gpio, pin_ll, altf);
} else {
LL_GPIO_SetAFPin_8_15(gpio, pin_ll, altf);
}
}
LL_GPIO_SetPinMode(gpio, pin_ll, mode >> STM32_MODER_SHIFT);
z_stm32_hsem_unlock(CFG_HW_GPIO_SEMID);
#endif /* CONFIG_SOC_SERIES_STM32F1X */