diff --git a/boards/others/neorv32/doc/index.rst b/boards/others/neorv32/doc/index.rst index d9a76304c15..89f74016c9a 100644 --- a/boards/others/neorv32/doc/index.rst +++ b/boards/others/neorv32/doc/index.rst @@ -13,7 +13,7 @@ For more information about the NEORV32, see the following websites: - `The NEORV32 RISC-V Processor Datasheet`_ - `The NEORV32 RISC-V Processor User Guide`_ -The currently supported version is NEORV32 v1.11.2. +The currently supported version is NEORV32 v1.11.3. Supported Board Targets ======================= diff --git a/doc/releases/migration-guide-4.2.rst b/doc/releases/migration-guide-4.2.rst index d8ef656d51b..8ef5726d065 100644 --- a/doc/releases/migration-guide-4.2.rst +++ b/doc/releases/migration-guide-4.2.rst @@ -53,7 +53,7 @@ Boards * The DT binding :dtcompatible:`zephyr,native-posix-cpu` has been deprecated in favor of :dtcompatible:`zephyr,native-sim-cpu`. -* Zephyr now supports version 1.11.2 of the :zephyr:board:`neorv32`. NEORV32 processor (SoC) +* Zephyr now supports version 1.11.3 of the :zephyr:board:`neorv32`. NEORV32 processor (SoC) implementations need to be updated to this version to be compatible with Zephyr v4.2.0. * The :zephyr:board:`neorv32` now targets NEORV32 processor (SoC) templates via board variants. The diff --git a/soc/neorv32/Kconfig b/soc/neorv32/Kconfig index bba678a61c7..4d3424a8358 100644 --- a/soc/neorv32/Kconfig +++ b/soc/neorv32/Kconfig @@ -13,7 +13,7 @@ if SOC_NEORV32 config SOC_NEORV32_VERSION hex - default 0x01110200 + default 0x01110300 help The targeted NEORV32 version as BCD-coded number. The format is identical to that of the NEORV32 Machine implementation ID (mimpid) diff --git a/soc/neorv32/soc.h b/soc/neorv32/soc.h index 1e31ec1e6d0..a095bf49b7f 100644 --- a/soc/neorv32/soc.h +++ b/soc/neorv32/soc.h @@ -20,34 +20,35 @@ #define NEORV32_SYSINFO_MISC_BOOT GENMASK(31, 24) /* System information (SYSINFO) SOC register bits */ -#define NEORV32_SYSINFO_SOC_BOOTLOADER BIT(0) -#define NEORV32_SYSINFO_SOC_XBUS BIT(1) -#define NEORV32_SYSINFO_SOC_MEM_INT_IMEM BIT(2) -#define NEORV32_SYSINFO_SOC_MEM_INT_DMEM BIT(3) -#define NEORV32_SYSINFO_SOC_OCD BIT(4) -#define NEORV32_SYSINFO_SOC_ICACHE BIT(5) -#define NEORV32_SYSINFO_SOC_DCACHE BIT(6) -#define NEORV32_SYSINFO_SOC_XBUS_CACHE BIT(8) -#define NEORV32_SYSINFO_SOC_OCD_AUTH BIT(11) -#define NEORV32_SYSINFO_SOC_IMEM_ROM BIT(12) -#define NEORV32_SYSINFO_SOC_IO_TWD BIT(13) -#define NEORV32_SYSINFO_SOC_IO_DMA BIT(14) -#define NEORV32_SYSINFO_SOC_IO_GPIO BIT(15) -#define NEORV32_SYSINFO_SOC_IO_CLINT BIT(16) -#define NEORV32_SYSINFO_SOC_IO_UART0 BIT(17) -#define NEORV32_SYSINFO_SOC_IO_SPI BIT(18) -#define NEORV32_SYSINFO_SOC_IO_TWI BIT(19) -#define NEORV32_SYSINFO_SOC_IO_PWM BIT(20) -#define NEORV32_SYSINFO_SOC_IO_WDT BIT(21) -#define NEORV32_SYSINFO_SOC_IO_CFS BIT(22) -#define NEORV32_SYSINFO_SOC_IO_TRNG BIT(23) -#define NEORV32_SYSINFO_SOC_IO_SDI BIT(24) -#define NEORV32_SYSINFO_SOC_IO_UART1 BIT(25) -#define NEORV32_SYSINFO_SOC_IO_NEOLED BIT(26) -#define NEORV32_SYSINFO_SOC_IO_GPTMR BIT(28) -#define NEORV32_SYSINFO_SOC_IO_SLINK BIT(29) -#define NEORV32_SYSINFO_SOC_IO_ONEWIRE BIT(30) -#define NEORV32_SYSINFO_SOC_IO_CRC BIT(31) +#define NEORV32_SYSINFO_SOC_BOOTLOADER BIT(0) +#define NEORV32_SYSINFO_SOC_XBUS BIT(1) +#define NEORV32_SYSINFO_SOC_MEM_INT_IMEM BIT(2) +#define NEORV32_SYSINFO_SOC_MEM_INT_DMEM BIT(3) +#define NEORV32_SYSINFO_SOC_OCD BIT(4) +#define NEORV32_SYSINFO_SOC_ICACHE BIT(5) +#define NEORV32_SYSINFO_SOC_DCACHE BIT(6) +#define NEORV32_SYSINFO_SOC_XBUS_CACHE BIT(8) +#define NEORV32_SYSINFO_SOC_OCD_AUTH BIT(11) +#define NEORV32_SYSINFO_SOC_IMEM_ROM BIT(12) +#define NEORV32_SYSINFO_SOC_IO_TWD BIT(13) +#define NEORV32_SYSINFO_SOC_IO_DMA BIT(14) +#define NEORV32_SYSINFO_SOC_IO_GPIO BIT(15) +#define NEORV32_SYSINFO_SOC_IO_CLINT BIT(16) +#define NEORV32_SYSINFO_SOC_IO_UART0 BIT(17) +#define NEORV32_SYSINFO_SOC_IO_SPI BIT(18) +#define NEORV32_SYSINFO_SOC_IO_TWI BIT(19) +#define NEORV32_SYSINFO_SOC_IO_PWM BIT(20) +#define NEORV32_SYSINFO_SOC_IO_WDT BIT(21) +#define NEORV32_SYSINFO_SOC_IO_CFS BIT(22) +#define NEORV32_SYSINFO_SOC_IO_TRNG BIT(23) +#define NEORV32_SYSINFO_SOC_IO_SDI BIT(24) +#define NEORV32_SYSINFO_SOC_IO_UART1 BIT(25) +#define NEORV32_SYSINFO_SOC_IO_NEOLED BIT(26) +#define NEORV32_SYSINFO_SOC_IO_HWSPINLOCK BIT(27) +#define NEORV32_SYSINFO_SOC_IO_GPTMR BIT(28) +#define NEORV32_SYSINFO_SOC_IO_SLINK BIT(29) +#define NEORV32_SYSINFO_SOC_IO_ONEWIRE BIT(30) +#define NEORV32_SYSINFO_SOC_IO_CRC BIT(31) /* System information (SYSINFO) CACHE register bits */ #define NEORV32_SYSINFO_CACHE_INST_BLOCK_SIZE GENMASK(3, 0)