boards: x86: acrn_ehl_crb: add APIC timer TSC M and N
The acrn_ehl_crb used the APIC timer but did not configure the TSC M and N parameters, which are advised where available. This adds the values consistent with native (ehl_crb) definition. Signed-off-by: Jennifer Williams <jennifer.m.williams@intel.com>
This commit is contained in:
parent
cb1ac9e925
commit
027ce3d458
1 changed files with 2 additions and 0 deletions
|
@ -16,3 +16,5 @@ CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n
|
|||
CONFIG_KERNEL_VM_SIZE=0x1000000
|
||||
CONFIG_BUILD_NO_GAP_FILL=y
|
||||
CONFIG_APIC_TIMER_IRQ=48
|
||||
CONFIG_APIC_TIMER_TSC_M=3
|
||||
CONFIG_APIC_TIMER_TSC_N=249
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue