intel_s1000: add intel_s1000_crb board
intel_s1000_crb board makes use of the intel_s1000 SoC. It has a built-in ROM which gets executed upon applying power. It then executes the secondary bootloader followed by the FW (like zephyr). Change-Id: If334c359b4372a56997c3b2e1eb9250e80847f07 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Rajavardhan Gundi
Anas Nashif
parent
0090fd4d15
commit
02736e5935
6 changed files with 453 additions and 420 deletions
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@ -1,5 +1,6 @@
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/*
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/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@ -7,222 +8,301 @@
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* @file
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* @file
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* @brief Linker command/script file
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* @brief Linker command/script file
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*
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*
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* Linker script for the Xtensa platform.
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* Linker script for the intel_s1000_crb platform
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*/
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*/
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OUTPUT_ARCH(xtensa)
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#define _LINKER
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#define _LINKER
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#define _ASMLANGUAGE
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#define _ASMLANGUAGE
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#include "memory.h"
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#include <autoconf.h>
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#include <autoconf.h>
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#include <linker/sections.h>
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#include <linker/sections.h>
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#include <linker/linker-defs.h>
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#include <linker/linker-defs.h>
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#include <linker/linker-tool.h>
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#include <linker/linker-tool.h>
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#define RAMABLE_REGION sram0_seg :sram0_phdr
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#define RAMABLE_REGION data :data_phdr
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#define ROMABLE_REGION srom1_seg :srom1_phdr
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#define ROMABLE_REGION text :text_phdr
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MEMORY
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MEMORY
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{
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{
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sram0_seg : org = 0x80000000, len = 0x3EFE0000
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vector_reset_text :
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srom0_seg : org = 0xBEFE0000, len = 0x300
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org = XCHAL_RESET_VECTOR0_PADDR_SRAM,
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srom1_seg : org = 0xBEFE0300, len = 0x100
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len = MEM_RESET_TEXT_SIZE
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srom2_seg : org = 0xBEFE0400, len = 0x180
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vector_reset_lit :
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srom4_seg : org = 0xBEFE0800, len = 0x178
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org = XCHAL_RESET_VECTOR0_PADDR_SRAM + MEM_RESET_TEXT_SIZE,
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srom5_seg : org = 0xBEFE0978, len = 0x8
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len = MEM_RESET_LIT_SIZE
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srom6_seg : org = 0xBEFE0980, len = 0x38
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vector_memory_lit :
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srom7_seg : org = 0xBEFE09B8, len = 0x8
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org = XCHAL_MEMERROR_VECTOR_PADDR + MEM_ERROR_LIT_SIZE,
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srom8_seg : org = 0xBEFE09C0, len = 0x38
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len = MEM_ERROR_LIT_SIZE
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srom9_seg : org = 0xBEFE09F8, len = 0x8
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vector_memory_text :
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srom10_seg : org = 0xBEFE0A00, len = 0x38
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org = XCHAL_MEMERROR_VECTOR_PADDR,
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srom11_seg : org = 0xBEFE0A38, len = 0x8
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len = MEM_ERROR_TEXT_SIZE
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srom12_seg : org = 0xBEFE0A40, len = 0x38
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vector_base_text :
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srom13_seg : org = 0xBEFE0A78, len = 0x8
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org = XCHAL_VECBASE_RESET_PADDR_SRAM,
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srom14_seg : org = 0xBEFE0A80, len = 0x38
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len = MEM_VECBASE_LIT_SIZE
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srom15_seg : org = 0xBEFE0AB8, len = 0x8
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vector_int2_lit :
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srom16_seg : org = 0xBEFE0AC0, len = 0x38
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org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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srom17_seg : org = 0xBEFE0AF8, len = 0x8
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len = MEM_VECT_LIT_SIZE
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srom18_seg : org = 0xBEFE0B00, len = 0x38
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vector_int2_text :
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srom19_seg : org = 0xBEFE0B38, len = 0x8
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org = XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM,
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srom20_seg : org = 0xBEFE0B40, len = 0x38
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len = MEM_VECT_TEXT_SIZE
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srom21_seg : org = 0xBEFE0B78, len = 0x48
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vector_int3_lit :
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srom22_seg : org = 0xBEFE0BC0, len = 0x40
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org = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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srom23_seg : org = 0xBEFE0C00, len = 0x1D400
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len = MEM_VECT_LIT_SIZE
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vector_int3_text :
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org = XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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vector_int4_lit :
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org = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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len = MEM_VECT_LIT_SIZE
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vector_int4_text :
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org = XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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vector_int5_lit :
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org = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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len = MEM_VECT_LIT_SIZE
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vector_int5_text :
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org = XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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vector_int6_lit :
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org = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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len = MEM_VECT_LIT_SIZE
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vector_int6_text :
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org = XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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vector_int7_lit :
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org = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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len = MEM_VECT_LIT_SIZE
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vector_int7_text :
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org = XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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vector_kernel_lit :
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org = XCHAL_KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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len = MEM_VECT_LIT_SIZE
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vector_kernel_text :
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org = XCHAL_KERNEL_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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vector_user_lit :
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org = XCHAL_USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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len = MEM_VECT_LIT_SIZE
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vector_user_text :
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org = XCHAL_USER_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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vector_double_lit :
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org = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE,
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len = MEM_VECT_LIT_SIZE
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vector_double_text :
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org = XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM,
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len = MEM_VECT_TEXT_SIZE
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text :
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org = TEXT_BASE,
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len = TEXT_SIZE,
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#ifdef CONFIG_GEN_ISR_TABLES
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xBEFFE000, len = 0x2000
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IDT_LIST :
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org = TEXT_BASE + TEXT_SIZE,
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len = IDT_SIZE,
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#endif
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#endif
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data :
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org = TEXT_BASE + TEXT_SIZE + IDT_SIZE,
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len = DATA_SIZE
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bss_data :
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org = TEXT_BASE + TEXT_SIZE + IDT_SIZE + DATA_SIZE,
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len = BSS_DATA_SIZE
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}
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}
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PHDRS
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PHDRS
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{
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{
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sram0_phdr PT_LOAD;
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vector_reset_text_phdr PT_LOAD;
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sram0_bss_phdr PT_LOAD;
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vector_reset_lit_phdr PT_LOAD;
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srom0_phdr PT_LOAD;
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vector_memory_lit_phdr PT_LOAD;
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srom1_phdr PT_LOAD;
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vector_memory_text_phdr PT_LOAD;
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srom2_phdr PT_LOAD;
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vector_base_text_phdr PT_LOAD;
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srom3_phdr PT_LOAD;
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vector_int2_lit_phdr PT_LOAD;
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srom4_phdr PT_LOAD;
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vector_int2_text_phdr PT_LOAD;
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srom5_phdr PT_LOAD;
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vector_int3_lit_phdr PT_LOAD;
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srom6_phdr PT_LOAD;
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vector_int3_text_phdr PT_LOAD;
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srom7_phdr PT_LOAD;
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vector_int4_lit_phdr PT_LOAD;
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srom8_phdr PT_LOAD;
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vector_int4_text_phdr PT_LOAD;
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srom9_phdr PT_LOAD;
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vector_int5_lit_phdr PT_LOAD;
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srom10_phdr PT_LOAD;
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vector_int5_text_phdr PT_LOAD;
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srom11_phdr PT_LOAD;
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vector_int6_lit_phdr PT_LOAD;
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srom12_phdr PT_LOAD;
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vector_int6_text_phdr PT_LOAD;
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srom13_phdr PT_LOAD;
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vector_int7_lit_phdr PT_LOAD;
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srom14_phdr PT_LOAD;
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vector_int7_text_phdr PT_LOAD;
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srom15_phdr PT_LOAD;
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vector_kernel_lit_phdr PT_LOAD;
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srom16_phdr PT_LOAD;
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vector_kernel_text_phdr PT_LOAD;
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srom17_phdr PT_LOAD;
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vector_user_lit_phdr PT_LOAD;
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srom18_phdr PT_LOAD;
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vector_user_text_phdr PT_LOAD;
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srom19_phdr PT_LOAD;
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vector_double_lit_phdr PT_LOAD;
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srom20_phdr PT_LOAD;
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vector_double_text_phdr PT_LOAD;
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srom21_phdr PT_LOAD;
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text_phdr PT_LOAD;
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srom22_phdr PT_LOAD;
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data_phdr PT_LOAD;
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srom23_phdr PT_LOAD;
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bss_data_phdr PT_LOAD;
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}
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}
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/* Default entry point: */
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ENTRY(_ResetVector)
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/* Memory boundary addresses: */
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_memmap_mem_sram_start = 0x80000000;
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_memmap_mem_sram_end = 0xbefe0000;
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_memmap_mem_srom_start = 0xbefe0000;
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_memmap_mem_srom_end = 0xbf000000;
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/* Memory segment boundary addresses: */
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_memmap_seg_sram0_start = 0x80000000;
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_memmap_seg_sram0_max = 0xbefe0000;
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_memmap_seg_srom0_start = 0xbefe0000;
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_memmap_seg_srom0_max = 0xbefe0300;
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_memmap_seg_srom1_start = 0xbefe0300;
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_memmap_seg_srom1_max = 0xbefe0400;
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_memmap_seg_srom2_start = 0xbefe0400;
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_memmap_seg_srom2_max = 0xbefe0580;
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_memmap_seg_srom4_start = 0xbefe0800;
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_memmap_seg_srom4_max = 0xbefe0978;
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_memmap_seg_srom5_start = 0xbefe0978;
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_memmap_seg_srom5_max = 0xbefe0980;
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_memmap_seg_srom6_start = 0xbefe0980;
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_memmap_seg_srom6_max = 0xbefe09b8;
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_memmap_seg_srom7_start = 0xbefe09b8;
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_memmap_seg_srom7_max = 0xbefe09c0;
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_memmap_seg_srom8_start = 0xbefe09c0;
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_memmap_seg_srom8_max = 0xbefe09f8;
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_memmap_seg_srom9_start = 0xbefe09f8;
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_memmap_seg_srom9_max = 0xbefe0a00;
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_memmap_seg_srom10_start = 0xbefe0a00;
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_memmap_seg_srom10_max = 0xbefe0a38;
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_memmap_seg_srom11_start = 0xbefe0a38;
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_memmap_seg_srom11_max = 0xbefe0a40;
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_memmap_seg_srom12_start = 0xbefe0a40;
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_memmap_seg_srom12_max = 0xbefe0a78;
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_memmap_seg_srom13_start = 0xbefe0a78;
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_memmap_seg_srom13_max = 0xbefe0a80;
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_memmap_seg_srom14_start = 0xbefe0a80;
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_memmap_seg_srom14_max = 0xbefe0ab8;
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_memmap_seg_srom15_start = 0xbefe0ab8;
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_memmap_seg_srom15_max = 0xbefe0ac0;
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_memmap_seg_srom16_start = 0xbefe0ac0;
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_memmap_seg_srom16_max = 0xbefe0af8;
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_memmap_seg_srom17_start = 0xbefe0af8;
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_memmap_seg_srom17_max = 0xbefe0b00;
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_memmap_seg_srom18_start = 0xbefe0b00;
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_memmap_seg_srom18_max = 0xbefe0b38;
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_memmap_seg_srom19_start = 0xbefe0b38;
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_memmap_seg_srom19_max = 0xbefe0b40;
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_memmap_seg_srom20_start = 0xbefe0b40;
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_memmap_seg_srom20_max = 0xbefe0b78;
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_memmap_seg_srom21_start = 0xbefe0b78;
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_memmap_seg_srom21_max = 0xbefe0bc0;
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_memmap_seg_srom22_start = 0xbefe0bc0;
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_memmap_seg_srom22_max = 0xbefe0c00;
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_memmap_seg_srom23_start = 0xbefe0c00;
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_memmap_seg_srom23_max = 0xbf000000;
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_rom_store_table = 0;
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_rom_store_table = 0;
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PROVIDE(_memmap_vecbase_reset = 0xbefe0800);
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PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
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PROVIDE(_memmap_reset_vector = 0xbefe0000);
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/* Various memory-map dependent cache attribute settings: */
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_memmap_cacheattr_wb_base = 0x00440000;
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_memmap_cacheattr_wt_base = 0x00110000;
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_memmap_cacheattr_bp_base = 0x00220000;
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_memmap_cacheattr_unused_mask = 0xFF00FFFF;
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_memmap_cacheattr_wb_trapnull = 0x2244222F;
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_memmap_cacheattr_wba_trapnull = 0x2244222F;
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_memmap_cacheattr_wbna_trapnull = 0x2255222F;
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_memmap_cacheattr_wt_trapnull = 0x2211222F;
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_memmap_cacheattr_bp_trapnull = 0x2222222F;
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_memmap_cacheattr_wb_strict = 0xFF44FFFF;
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_memmap_cacheattr_wt_strict = 0xFF11FFFF;
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_memmap_cacheattr_bp_strict = 0xFF22FFFF;
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_memmap_cacheattr_wb_allvalid = 0x22442222;
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_memmap_cacheattr_wt_allvalid = 0x22112222;
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_memmap_cacheattr_bp_allvalid = 0x22222222;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
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/* Various memory-map dependent cache attribute settings: */
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_memmap_cacheattr_wb_base = 0x44024000;
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_memmap_cacheattr_wt_base = 0x11021000;
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_memmap_cacheattr_bp_base = 0x22022000;
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_memmap_cacheattr_unused_mask = 0x00F00FFF;
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_memmap_cacheattr_wb_trapnull = 0x4422422F;
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_memmap_cacheattr_wba_trapnull = 0x4422422F;
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_memmap_cacheattr_wbna_trapnull = 0x25222222;
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_memmap_cacheattr_wt_trapnull = 0x1122122F;
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_memmap_cacheattr_bp_trapnull = 0x2222222F;
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_memmap_cacheattr_wb_strict = 0x44F24FFF;
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_memmap_cacheattr_wt_strict = 0x11F21FFF;
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_memmap_cacheattr_bp_strict = 0x22F22FFF;
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_memmap_cacheattr_wb_allvalid = 0x44224222;
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_memmap_cacheattr_wt_allvalid = 0x11221222;
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_memmap_cacheattr_bp_allvalid = 0x22222222;
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_memmap_cacheattr_intel_s1000 = 0xf2ff4242;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_s1000);
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SECTIONS
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SECTIONS
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{
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{
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.ResetVector.text : ALIGN(4)
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.sram.rodata : ALIGN(4)
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{
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{
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_image_ram_start = ABSOLUTE(.);
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_ResetVector_text_start = ABSOLUTE(.);
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_sram_rodata_start = ABSOLUTE(.);
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KEEP (*(.ResetVector.text))
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*(.sram.rodata)
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_ResetVector_text_end = ABSOLUTE(.);
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_sram_rodata_end = ABSOLUTE(.);
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} >vector_reset_text :vector_reset_text_phdr
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} >sram0_seg :sram0_phdr
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.ResetVector.literal : ALIGN(4)
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#include <linker/common-rom.ld>
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.rodata : ALIGN(4)
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{
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{
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_rodata_start = ABSOLUTE(.);
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_ResetVector_literal_start = ABSOLUTE(.);
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*(.rodata)
|
*(.ResetVector.literal)
|
||||||
*(.rodata.*)
|
_ResetVector_literal_end = ABSOLUTE(.);
|
||||||
*(.gnu.linkonce.r.*)
|
} >vector_reset_lit :vector_reset_lit_phdr
|
||||||
*(.rodata1)
|
.MemoryExceptionVector.literal : ALIGN(4)
|
||||||
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
|
|
||||||
KEEP (*(.xt_except_table))
|
|
||||||
KEEP (*(.gcc_except_table))
|
|
||||||
*(.gnu.linkonce.e.*)
|
|
||||||
*(.gnu.version_r)
|
|
||||||
KEEP (*(.eh_frame))
|
|
||||||
/* C++ constructor and destructor tables, properly ordered: */
|
|
||||||
KEEP (*crtbegin.o(.ctors))
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
|
||||||
KEEP (*(SORT(.ctors.*)))
|
|
||||||
KEEP (*(.ctors))
|
|
||||||
KEEP (*crtbegin.o(.dtors))
|
|
||||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
|
||||||
KEEP (*(SORT(.dtors.*)))
|
|
||||||
KEEP (*(.dtors))
|
|
||||||
/* C++ exception handlers table: */
|
|
||||||
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
|
|
||||||
*(.xt_except_desc)
|
|
||||||
*(.gnu.linkonce.h.*)
|
|
||||||
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
|
||||||
*(.xt_except_desc_end)
|
|
||||||
*(.dynamic)
|
|
||||||
*(.gnu.version_d)
|
|
||||||
. = ALIGN(4); /* this table MUST be 4-byte aligned */
|
|
||||||
_bss_table_start = ABSOLUTE(.);
|
|
||||||
LONG(_bss_start)
|
|
||||||
LONG(_bss_end)
|
|
||||||
_bss_table_end = ABSOLUTE(.);
|
|
||||||
_rodata_end = ABSOLUTE(.);
|
|
||||||
} >sram0_seg :sram0_phdr
|
|
||||||
|
|
||||||
.sram.text : ALIGN(4)
|
|
||||||
{
|
{
|
||||||
_sram_text_start = ABSOLUTE(.);
|
_MemoryExceptionVector_literal_start = ABSOLUTE(.);
|
||||||
*(.sram.literal .sram.text)
|
KEEP (*(.MemoryExceptionVector.literal))
|
||||||
_sram_text_end = ABSOLUTE(.);
|
_MemoryExceptionVector_literal_end = ABSOLUTE(.);
|
||||||
} >sram0_seg :sram0_phdr
|
} >vector_memory_lit :vector_memory_lit_phdr
|
||||||
|
.MemoryExceptionVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_MemoryExceptionVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.MemoryExceptionVector.text))
|
||||||
|
_MemoryExceptionVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_memory_text :vector_memory_text_phdr
|
||||||
|
.WindowVectors.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_WindowVectors_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.WindowVectors.text))
|
||||||
|
_WindowVectors_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_base_text :vector_base_text_phdr
|
||||||
|
.Level2InterruptVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_Level2InterruptVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.Level2InterruptVector.literal)
|
||||||
|
_Level2InterruptVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_int2_lit :vector_int2_lit_phdr
|
||||||
|
.Level2InterruptVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_Level2InterruptVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.Level2InterruptVector.text))
|
||||||
|
_Level2InterruptVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_int2_text :vector_int2_text_phdr
|
||||||
|
.Level3InterruptVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_Level3InterruptVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.Level3InterruptVector.literal)
|
||||||
|
_Level3InterruptVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_int3_lit :vector_int3_lit_phdr
|
||||||
|
.Level3InterruptVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_Level3InterruptVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.Level3InterruptVector.text))
|
||||||
|
_Level3InterruptVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_int3_text :vector_int3_text_phdr
|
||||||
|
.Level4InterruptVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_Level4InterruptVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.Level4InterruptVector.literal)
|
||||||
|
_Level4InterruptVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_int4_lit :vector_int4_lit_phdr
|
||||||
|
.Level4InterruptVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_Level4InterruptVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.Level4InterruptVector.text))
|
||||||
|
_Level4InterruptVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_int4_text :vector_int4_text_phdr
|
||||||
|
.Level5InterruptVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_Level5InterruptVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.Level5InterruptVector.literal)
|
||||||
|
_Level5InterruptVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_int5_lit :vector_int5_lit_phdr
|
||||||
|
.Level5InterruptVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_Level5InterruptVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.Level5InterruptVector.text))
|
||||||
|
_Level5InterruptVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_int5_text :vector_int5_text_phdr
|
||||||
|
.DebugExceptionVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_DebugExceptionVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.DebugExceptionVector.literal)
|
||||||
|
_DebugExceptionVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_int6_lit :vector_int6_lit_phdr
|
||||||
|
.DebugExceptionVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_DebugExceptionVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.DebugExceptionVector.text))
|
||||||
|
_DebugExceptionVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_int6_text :vector_int6_text_phdr
|
||||||
|
.NMIExceptionVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_NMIExceptionVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.NMIExceptionVector.literal)
|
||||||
|
_NMIExceptionVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_int7_lit :vector_int7_lit_phdr
|
||||||
|
.NMIExceptionVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_NMIExceptionVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.NMIExceptionVector.text))
|
||||||
|
_NMIExceptionVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_int7_text :vector_int7_text_phdr
|
||||||
|
.KernelExceptionVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_KernelExceptionVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.KernelExceptionVector.literal)
|
||||||
|
_KernelExceptionVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_kernel_lit :vector_kernel_lit_phdr
|
||||||
|
.KernelExceptionVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_KernelExceptionVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.KernelExceptionVector.text))
|
||||||
|
_KernelExceptionVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_kernel_text :vector_kernel_text_phdr
|
||||||
|
.UserExceptionVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_UserExceptionVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.UserExceptionVector.literal)
|
||||||
|
_UserExceptionVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_user_lit :vector_user_lit_phdr
|
||||||
|
.UserExceptionVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_UserExceptionVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.UserExceptionVector.text))
|
||||||
|
_UserExceptionVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_user_text :vector_user_text_phdr
|
||||||
|
.DoubleExceptionVector.literal : ALIGN(4)
|
||||||
|
{
|
||||||
|
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
|
||||||
|
*(.DoubleExceptionVector.literal)
|
||||||
|
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
|
||||||
|
} >vector_double_lit :vector_double_lit_phdr
|
||||||
|
.DoubleExceptionVector.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
_DoubleExceptionVector_text_start = ABSOLUTE(.);
|
||||||
|
KEEP (*(.DoubleExceptionVector.text))
|
||||||
|
_DoubleExceptionVector_text_end = ABSOLUTE(.);
|
||||||
|
} >vector_double_text :vector_double_text_phdr
|
||||||
|
|
||||||
_image_text_start = ALIGN(4);
|
|
||||||
.text : ALIGN(4)
|
.text : ALIGN(4)
|
||||||
{
|
{
|
||||||
_stext = .;
|
_stext = .;
|
||||||
|
|
@ -236,22 +316,49 @@ SECTIONS
|
||||||
*(.gnu.version)
|
*(.gnu.version)
|
||||||
_text_end = ABSOLUTE(.);
|
_text_end = ABSOLUTE(.);
|
||||||
_etext = .;
|
_etext = .;
|
||||||
} >sram0_seg :sram0_phdr
|
} >text :text_phdr
|
||||||
_image_text_end = .;
|
#include <linker/common-rom.ld>
|
||||||
|
|
||||||
.sram.data : ALIGN(4)
|
|
||||||
{
|
|
||||||
_sram_data_start = ABSOLUTE(.);
|
|
||||||
*(.sram.data)
|
|
||||||
_sram_data_end = ABSOLUTE(.);
|
|
||||||
} >sram0_seg :sram0_phdr
|
|
||||||
|
|
||||||
.noinit : ALIGN(4)
|
.noinit : ALIGN(4)
|
||||||
{
|
{
|
||||||
*(.noinit)
|
*(.noinit)
|
||||||
*(.noinit.*)
|
*(.noinit.*)
|
||||||
} >sram0_seg :sram0_phdr
|
} >data :data_phdr
|
||||||
|
.rodata : ALIGN(4)
|
||||||
|
{
|
||||||
|
_rodata_start = ABSOLUTE(.);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata.*)
|
||||||
|
*(.gnu.linkonce.r.*)
|
||||||
|
*(.rodata1)
|
||||||
|
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
|
||||||
|
KEEP (*(.xt_except_table))
|
||||||
|
KEEP (*(.gcc_except_table))
|
||||||
|
*(.gnu.linkonce.e.*)
|
||||||
|
*(.gnu.version_r)
|
||||||
|
KEEP (*(.eh_frame))
|
||||||
|
KEEP (*crtbegin.o(.ctors))
|
||||||
|
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||||
|
KEEP (*(SORT(.ctors.*)))
|
||||||
|
KEEP (*(.ctors))
|
||||||
|
KEEP (*crtbegin.o(.dtors))
|
||||||
|
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||||
|
KEEP (*(SORT(.dtors.*)))
|
||||||
|
KEEP (*(.dtors))
|
||||||
|
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
|
||||||
|
*(.xt_except_desc)
|
||||||
|
*(.gnu.linkonce.h.*)
|
||||||
|
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
|
||||||
|
*(.xt_except_desc_end)
|
||||||
|
*(.dynamic)
|
||||||
|
*(.gnu.version_d)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_bss_table_start = ABSOLUTE(.);
|
||||||
|
LONG(_bss_start)
|
||||||
|
LONG(_bss_end)
|
||||||
|
_bss_table_end = ABSOLUTE(.);
|
||||||
|
_rodata_end = ABSOLUTE(.);
|
||||||
|
} >data :data_phdr
|
||||||
.data : ALIGN(4)
|
.data : ALIGN(4)
|
||||||
{
|
{
|
||||||
_data_start = ABSOLUTE(.);
|
_data_start = ABSOLUTE(.);
|
||||||
|
|
@ -269,8 +376,15 @@ SECTIONS
|
||||||
*(.gnu.linkonce.s2.*)
|
*(.gnu.linkonce.s2.*)
|
||||||
KEEP(*(.jcr))
|
KEEP(*(.jcr))
|
||||||
_data_end = ABSOLUTE(.);
|
_data_end = ABSOLUTE(.);
|
||||||
} >sram0_seg :sram0_phdr
|
} >data :data_phdr
|
||||||
|
.lit4 : ALIGN(4)
|
||||||
|
{
|
||||||
|
_lit4_start = ABSOLUTE(.);
|
||||||
|
*(*.lit4)
|
||||||
|
*(.lit4.*)
|
||||||
|
*(.gnu.linkonce.lit4.*)
|
||||||
|
_lit4_end = ABSOLUTE(.);
|
||||||
|
} >data :data_phdr
|
||||||
#include <linker/common-ram.ld>
|
#include <linker/common-ram.ld>
|
||||||
|
|
||||||
.bss (NOLOAD) : ALIGN(8)
|
.bss (NOLOAD) : ALIGN(8)
|
||||||
|
|
@ -290,208 +404,14 @@ SECTIONS
|
||||||
*(.bss.*)
|
*(.bss.*)
|
||||||
*(.gnu.linkonce.b.*)
|
*(.gnu.linkonce.b.*)
|
||||||
*(COMMON)
|
*(COMMON)
|
||||||
*(.sram.bss)
|
|
||||||
. = ALIGN (8);
|
. = ALIGN (8);
|
||||||
_bss_end = ABSOLUTE(.);
|
_bss_end = ABSOLUTE(.);
|
||||||
_end = ALIGN(0x8);
|
} >bss_data :bss_data_phdr
|
||||||
_image_ram_end = ABSOLUTE(.);
|
|
||||||
PROVIDE(end = ALIGN(0x8));
|
|
||||||
_stack_sentry = ALIGN(0x8);
|
|
||||||
_memmap_seg_sram0_end = ALIGN(0x8);
|
|
||||||
} >sram0_seg :sram0_bss_phdr
|
|
||||||
__stack = 0xbefe0000;
|
|
||||||
_heap_sentry = 0xbefe0000;
|
|
||||||
|
|
||||||
.ResetVector.text : ALIGN(4)
|
/* stack */
|
||||||
{
|
_end = ALIGN(8);
|
||||||
_ResetVector_text_start = ABSOLUTE(.);
|
PROVIDE(end = ALIGN(8));
|
||||||
KEEP (*(.ResetVector.text))
|
__stack = L2_SRAM_BASE + L2_SRAM_SIZE;
|
||||||
_ResetVector_text_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom0_end = ALIGN(0x8);
|
|
||||||
} >srom0_seg :srom0_phdr
|
|
||||||
|
|
||||||
.MemoryExceptionVector.literal : ALIGN(4)
|
|
||||||
{
|
|
||||||
_MemoryExceptionVector_literal_start = ABSOLUTE(.);
|
|
||||||
*(.MemoryExceptionVector.literal)
|
|
||||||
_MemoryExceptionVector_literal_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom1_end = ALIGN(0x8);
|
|
||||||
} >srom1_seg :srom1_phdr
|
|
||||||
|
|
||||||
.MemoryExceptionVector.text : ALIGN(4)
|
|
||||||
{
|
|
||||||
_MemoryExceptionVector_text_start = ABSOLUTE(.);
|
|
||||||
KEEP (*(.MemoryExceptionVector.text))
|
|
||||||
_MemoryExceptionVector_text_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom2_end = ALIGN(0x8);
|
|
||||||
} >srom2_seg :srom2_phdr
|
|
||||||
|
|
||||||
.WindowVectors.text : ALIGN(4)
|
|
||||||
{
|
|
||||||
_WindowVectors_text_start = ABSOLUTE(.);
|
|
||||||
KEEP (*(.WindowVectors.text))
|
|
||||||
_WindowVectors_text_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom4_end = ALIGN(0x8);
|
|
||||||
} >srom4_seg :srom4_phdr
|
|
||||||
|
|
||||||
.Level2InterruptVector.literal : ALIGN(4)
|
|
||||||
{
|
|
||||||
_Level2InterruptVector_literal_start = ABSOLUTE(.);
|
|
||||||
*(.Level2InterruptVector.literal)
|
|
||||||
_Level2InterruptVector_literal_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom5_end = ALIGN(0x8);
|
|
||||||
} >srom5_seg :srom5_phdr
|
|
||||||
|
|
||||||
.Level2InterruptVector.text : ALIGN(4)
|
|
||||||
{
|
|
||||||
_Level2InterruptVector_text_start = ABSOLUTE(.);
|
|
||||||
KEEP (*(.Level2InterruptVector.text))
|
|
||||||
_Level2InterruptVector_text_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom6_end = ALIGN(0x8);
|
|
||||||
} >srom6_seg :srom6_phdr
|
|
||||||
|
|
||||||
.Level3InterruptVector.literal : ALIGN(4)
|
|
||||||
{
|
|
||||||
_Level3InterruptVector_literal_start = ABSOLUTE(.);
|
|
||||||
*(.Level3InterruptVector.literal)
|
|
||||||
_Level3InterruptVector_literal_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom7_end = ALIGN(0x8);
|
|
||||||
} >srom7_seg :srom7_phdr
|
|
||||||
|
|
||||||
.Level3InterruptVector.text : ALIGN(4)
|
|
||||||
{
|
|
||||||
_Level3InterruptVector_text_start = ABSOLUTE(.);
|
|
||||||
KEEP (*(.Level3InterruptVector.text))
|
|
||||||
_Level3InterruptVector_text_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom8_end = ALIGN(0x8);
|
|
||||||
} >srom8_seg :srom8_phdr
|
|
||||||
|
|
||||||
.Level4InterruptVector.literal : ALIGN(4)
|
|
||||||
{
|
|
||||||
_Level4InterruptVector_literal_start = ABSOLUTE(.);
|
|
||||||
*(.Level4InterruptVector.literal)
|
|
||||||
_Level4InterruptVector_literal_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom9_end = ALIGN(0x8);
|
|
||||||
} >srom9_seg :srom9_phdr
|
|
||||||
|
|
||||||
.Level4InterruptVector.text : ALIGN(4)
|
|
||||||
{
|
|
||||||
_Level4InterruptVector_text_start = ABSOLUTE(.);
|
|
||||||
KEEP (*(.Level4InterruptVector.text))
|
|
||||||
_Level4InterruptVector_text_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom10_end = ALIGN(0x8);
|
|
||||||
} >srom10_seg :srom10_phdr
|
|
||||||
|
|
||||||
.Level5InterruptVector.literal : ALIGN(4)
|
|
||||||
{
|
|
||||||
_Level5InterruptVector_literal_start = ABSOLUTE(.);
|
|
||||||
*(.Level5InterruptVector.literal)
|
|
||||||
_Level5InterruptVector_literal_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom11_end = ALIGN(0x8);
|
|
||||||
} >srom11_seg :srom11_phdr
|
|
||||||
|
|
||||||
.Level5InterruptVector.text : ALIGN(4)
|
|
||||||
{
|
|
||||||
_Level5InterruptVector_text_start = ABSOLUTE(.);
|
|
||||||
KEEP (*(.Level5InterruptVector.text))
|
|
||||||
_Level5InterruptVector_text_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom12_end = ALIGN(0x8);
|
|
||||||
} >srom12_seg :srom12_phdr
|
|
||||||
|
|
||||||
.DebugExceptionVector.literal : ALIGN(4)
|
|
||||||
{
|
|
||||||
_DebugExceptionVector_literal_start = ABSOLUTE(.);
|
|
||||||
*(.DebugExceptionVector.literal)
|
|
||||||
_DebugExceptionVector_literal_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom13_end = ALIGN(0x8);
|
|
||||||
} >srom13_seg :srom13_phdr
|
|
||||||
|
|
||||||
.DebugExceptionVector.text : ALIGN(4)
|
|
||||||
{
|
|
||||||
_DebugExceptionVector_text_start = ABSOLUTE(.);
|
|
||||||
KEEP (*(.DebugExceptionVector.text))
|
|
||||||
_DebugExceptionVector_text_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom14_end = ALIGN(0x8);
|
|
||||||
} >srom14_seg :srom14_phdr
|
|
||||||
|
|
||||||
.NMIExceptionVector.literal : ALIGN(4)
|
|
||||||
{
|
|
||||||
_NMIExceptionVector_literal_start = ABSOLUTE(.);
|
|
||||||
*(.NMIExceptionVector.literal)
|
|
||||||
_NMIExceptionVector_literal_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom15_end = ALIGN(0x8);
|
|
||||||
} >srom15_seg :srom15_phdr
|
|
||||||
|
|
||||||
.NMIExceptionVector.text : ALIGN(4)
|
|
||||||
{
|
|
||||||
_NMIExceptionVector_text_start = ABSOLUTE(.);
|
|
||||||
KEEP (*(.NMIExceptionVector.text))
|
|
||||||
_NMIExceptionVector_text_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom16_end = ALIGN(0x8);
|
|
||||||
} >srom16_seg :srom16_phdr
|
|
||||||
|
|
||||||
.KernelExceptionVector.literal : ALIGN(4)
|
|
||||||
{
|
|
||||||
_KernelExceptionVector_literal_start = ABSOLUTE(.);
|
|
||||||
*(.KernelExceptionVector.literal)
|
|
||||||
_KernelExceptionVector_literal_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom17_end = ALIGN(0x8);
|
|
||||||
} >srom17_seg :srom17_phdr
|
|
||||||
|
|
||||||
.KernelExceptionVector.text : ALIGN(4)
|
|
||||||
{
|
|
||||||
_KernelExceptionVector_text_start = ABSOLUTE(.);
|
|
||||||
KEEP (*(.KernelExceptionVector.text))
|
|
||||||
_KernelExceptionVector_text_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom18_end = ALIGN(0x8);
|
|
||||||
} >srom18_seg :srom18_phdr
|
|
||||||
|
|
||||||
.UserExceptionVector.literal : ALIGN(4)
|
|
||||||
{
|
|
||||||
_UserExceptionVector_literal_start = ABSOLUTE(.);
|
|
||||||
*(.UserExceptionVector.literal)
|
|
||||||
_UserExceptionVector_literal_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom19_end = ALIGN(0x8);
|
|
||||||
} >srom19_seg :srom19_phdr
|
|
||||||
|
|
||||||
.UserExceptionVector.text : ALIGN(4)
|
|
||||||
{
|
|
||||||
_UserExceptionVector_text_start = ABSOLUTE(.);
|
|
||||||
KEEP (*(.UserExceptionVector.text))
|
|
||||||
_UserExceptionVector_text_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom20_end = ALIGN(0x8);
|
|
||||||
} >srom20_seg :srom20_phdr
|
|
||||||
|
|
||||||
.DoubleExceptionVector.literal : ALIGN(4)
|
|
||||||
{
|
|
||||||
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
|
|
||||||
*(.DoubleExceptionVector.literal)
|
|
||||||
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom21_end = ALIGN(0x8);
|
|
||||||
} >srom21_seg :srom21_phdr
|
|
||||||
|
|
||||||
.DoubleExceptionVector.text : ALIGN(4)
|
|
||||||
{
|
|
||||||
_DoubleExceptionVector_text_start = ABSOLUTE(.);
|
|
||||||
KEEP (*(.DoubleExceptionVector.text))
|
|
||||||
_DoubleExceptionVector_text_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom22_end = ALIGN(0x8);
|
|
||||||
} >srom22_seg :srom22_phdr
|
|
||||||
|
|
||||||
.srom.rodata : ALIGN(4)
|
|
||||||
{
|
|
||||||
_srom_rodata_start = ABSOLUTE(.);
|
|
||||||
*(.srom.rodata)
|
|
||||||
_srom_rodata_end = ABSOLUTE(.);
|
|
||||||
} >srom23_seg :srom23_phdr
|
|
||||||
|
|
||||||
.srom.text : ALIGN(4)
|
|
||||||
{
|
|
||||||
_srom_text_start = ABSOLUTE(.);
|
|
||||||
*(.srom.literal .srom.text)
|
|
||||||
_srom_text_end = ABSOLUTE(.);
|
|
||||||
_memmap_seg_srom23_end = ALIGN(0x8);
|
|
||||||
} >srom23_seg :srom23_phdr
|
|
||||||
.debug 0 : { *(.debug) }
|
.debug 0 : { *(.debug) }
|
||||||
.line 0 : { *(.line) }
|
.line 0 : { *(.line) }
|
||||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||||
|
|
@ -526,12 +446,22 @@ SECTIONS
|
||||||
KEEP (*(.xt.lit.*))
|
KEEP (*(.xt.lit.*))
|
||||||
KEEP (*(.gnu.linkonce.p.*))
|
KEEP (*(.gnu.linkonce.p.*))
|
||||||
}
|
}
|
||||||
.debug.xt.callgraph 0 :
|
.xt.profile_range 0 :
|
||||||
{
|
{
|
||||||
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
|
KEEP (*(.xt.profile_range))
|
||||||
|
KEEP (*(.gnu.linkonce.profile_range.*))
|
||||||
|
}
|
||||||
|
.xt.profile_ranges 0 :
|
||||||
|
{
|
||||||
|
KEEP (*(.xt.profile_ranges))
|
||||||
|
KEEP (*(.gnu.linkonce.xt.profile_ranges.*))
|
||||||
|
}
|
||||||
|
.xt.profile_files 0 :
|
||||||
|
{
|
||||||
|
KEEP (*(.xt.profile_files))
|
||||||
|
KEEP (*(.gnu.linkonce.xt.profile_files.*))
|
||||||
}
|
}
|
||||||
#ifdef CONFIG_GEN_ISR_TABLES
|
#ifdef CONFIG_GEN_ISR_TABLES
|
||||||
#include <linker/intlist.ld>
|
#include <linker/intlist.ld>
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
61
arch/xtensa/soc/intel_s1000/memory.h
Normal file
61
arch/xtensa/soc/intel_s1000/memory.h
Normal file
|
|
@ -0,0 +1,61 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017 Intel Corporation
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __INC_MEMORY_H
|
||||||
|
#define __INC_MEMORY_H
|
||||||
|
|
||||||
|
/* L2 HP SRAM */
|
||||||
|
#define L2_SRAM_BASE 0xBE000000
|
||||||
|
#define L2_SRAM_SIZE 0x00300000
|
||||||
|
#define L2_VECTOR_SIZE 0x1000
|
||||||
|
|
||||||
|
/* The reset vector address in SRAM and its size */
|
||||||
|
#define XCHAL_RESET_VECTOR0_PADDR_SRAM L2_SRAM_BASE
|
||||||
|
#define MEM_RESET_TEXT_SIZE 0x268
|
||||||
|
#define MEM_RESET_LIT_SIZE 0x8
|
||||||
|
|
||||||
|
/* This is the base address of all the vectors defined in SRAM */
|
||||||
|
#define XCHAL_VECBASE_RESET_PADDR_SRAM (L2_SRAM_BASE + 0x400)
|
||||||
|
#define MEM_VECBASE_LIT_SIZE 0x178
|
||||||
|
|
||||||
|
/* The addresses of the vectors in SRAM.
|
||||||
|
* Only the memerror vector continues to point to its ROM address.
|
||||||
|
*/
|
||||||
|
#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x580)
|
||||||
|
#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x5C0)
|
||||||
|
#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x600)
|
||||||
|
#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x640)
|
||||||
|
#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x680)
|
||||||
|
#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x6C0)
|
||||||
|
#define XCHAL_KERNEL_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x700)
|
||||||
|
#define XCHAL_USER_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x740)
|
||||||
|
#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x7C0)
|
||||||
|
|
||||||
|
/* Vector and literal sizes */
|
||||||
|
#define MEM_VECT_LIT_SIZE 0x8
|
||||||
|
#define MEM_VECT_TEXT_SIZE 0x38
|
||||||
|
#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\
|
||||||
|
MEM_VECT_LIT_SIZE)
|
||||||
|
|
||||||
|
/* The memerror vector address is copied as is from core-isa.h */
|
||||||
|
#define XCHAL_MEMERROR_VECTOR_PADDR 0xBEFE0400
|
||||||
|
|
||||||
|
#define MEM_ERROR_TEXT_SIZE 0x180
|
||||||
|
#define MEM_ERROR_LIT_SIZE 0x8
|
||||||
|
|
||||||
|
/* text and data share the same L2 HP SRAM on Intel S1000 */
|
||||||
|
#define TEXT_BASE (L2_SRAM_BASE + L2_VECTOR_SIZE)
|
||||||
|
#define TEXT_SIZE 0x16000
|
||||||
|
|
||||||
|
/* size of the Interrupt Descriptor Table (IDT) */
|
||||||
|
#define IDT_SIZE 0x2000
|
||||||
|
|
||||||
|
/* initialized data */
|
||||||
|
#define DATA_SIZE 0x10000
|
||||||
|
|
||||||
|
/* bss data */
|
||||||
|
#define BSS_DATA_SIZE 0x8000
|
||||||
|
|
||||||
|
#endif /* __INC_MEMORY_H */
|
||||||
8
boards/xtensa/intel_s1000_crb/Kconfig.board
Normal file
8
boards/xtensa/intel_s1000_crb/Kconfig.board
Normal file
|
|
@ -0,0 +1,8 @@
|
||||||
|
# Kconfig - XTENSA board configuration
|
||||||
|
#
|
||||||
|
# Copyright (c) 2017 Intel Corporation
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
|
||||||
|
config BOARD_INTEL_S1000_CRB
|
||||||
|
bool "Xtensa on Intel_S1000"
|
||||||
|
depends on SOC_INTEL_S1000
|
||||||
13
boards/xtensa/intel_s1000_crb/Kconfig.defconfig
Normal file
13
boards/xtensa/intel_s1000_crb/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,13 @@
|
||||||
|
# Copyright (c) 2017 Intel Corporation
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: Apache-2.0
|
||||||
|
|
||||||
|
if BOARD_INTEL_S1000_CRB
|
||||||
|
|
||||||
|
config BOARD
|
||||||
|
default intel_s1000_crb
|
||||||
|
|
||||||
|
config BOARD_XTENSA
|
||||||
|
def_bool y
|
||||||
|
|
||||||
|
endif # BOARD_INTEL_S1000_CRB
|
||||||
6
boards/xtensa/intel_s1000_crb/intel_s1000_crb.yaml
Normal file
6
boards/xtensa/intel_s1000_crb/intel_s1000_crb.yaml
Normal file
|
|
@ -0,0 +1,6 @@
|
||||||
|
identifier: intel_s1000_crb
|
||||||
|
name: Intel S1000 using CAVS (Connected Audio Voice and Speech)
|
||||||
|
type: mcu
|
||||||
|
arch: xtensa
|
||||||
|
toolchain:
|
||||||
|
- xcc
|
||||||
15
boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig
Normal file
15
boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig
Normal file
|
|
@ -0,0 +1,15 @@
|
||||||
|
CONFIG_MAIN_STACK_SIZE=2048
|
||||||
|
CONFIG_IPM_CONSOLE_STACK_SIZE=2048
|
||||||
|
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=400000000
|
||||||
|
|
||||||
|
CONFIG_XTENSA=y
|
||||||
|
CONFIG_SOC_INTEL_S1000=y
|
||||||
|
CONFIG_BOARD_XTENSA=y
|
||||||
|
CONFIG_BOARD_INTEL_S1000_CRB=y
|
||||||
|
|
||||||
|
CONFIG_SW_ISR_TABLE=y
|
||||||
|
CONFIG_GEN_ISR_TABLES=y
|
||||||
|
CONFIG_GEN_IRQ_VECTOR_TABLE=n
|
||||||
|
|
||||||
|
CONFIG_XTENSA_RESET_VECTOR=y
|
||||||
|
CONFIG_XTENSA_USE_CORE_CRT1=y
|
||||||
Loading…
Add table
Add a link
Reference in a new issue