diff --git a/boards/arc/iotdk/CMakeLists.txt b/boards/arc/iotdk/CMakeLists.txt new file mode 100644 index 00000000000..ba9f9e45f8f --- /dev/null +++ b/boards/arc/iotdk/CMakeLists.txt @@ -0,0 +1 @@ +zephyr_sources_ifdef(CONFIG_ARC_MPU_ENABLE arc_mpu_regions.c) diff --git a/boards/arc/iotdk/Kconfig.board b/boards/arc/iotdk/Kconfig.board new file mode 100644 index 00000000000..57d642770a7 --- /dev/null +++ b/boards/arc/iotdk/Kconfig.board @@ -0,0 +1,11 @@ +# Kconfig - DesignWare ARC IoT Development Kit board configuration +# +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# +config BOARD_IOTDK + bool "ARC IoT Development Kit" + depends on SOC_ARC_IOT + help + The DesignWare ARC IoT Development Kit board is a versatile platform that includes the necessary hardware and software to accelerate software development and debugging of sensor fusion, voice recognition and face detection designs. It includes a silicon implementation of the ARC Data Fusion IP Subsystem running at 144 MHz on SMIC's 55-nm ultra-low power process, and a rich set of peripherals commonly used in IoT designs such as USB, UART, SPI, I2C, PWM, SDIO and ADCs. diff --git a/boards/arc/iotdk/Kconfig.defconfig b/boards/arc/iotdk/Kconfig.defconfig new file mode 100644 index 00000000000..7a9a0d834c2 --- /dev/null +++ b/boards/arc/iotdk/Kconfig.defconfig @@ -0,0 +1,10 @@ + +if BOARD_IOTDK + +config BOARD + default "iotdk" + +config CPU_ARCEM4 + def_bool y + +endif # BOARD_IOTDK diff --git a/boards/arc/iotdk/arc_mpu_regions.c b/boards/arc/iotdk/arc_mpu_regions.c new file mode 100644 index 00000000000..a31cf35777b --- /dev/null +++ b/boards/arc/iotdk/arc_mpu_regions.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2018 Synopsys + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#ifdef CONFIG_USERSPACE +static struct arc_mpu_region mpu_regions[] = { + /* Region ICCM */ + MPU_REGION_ENTRY("ICCM", + CONFIG_ICCM_BASE_ADDRESS, + CONFIG_ICCM_SIZE * 1024, + REGION_FLASH_ATTR), + /* Region DCCM */ + MPU_REGION_ENTRY("DCCM", + CONFIG_DCCM_BASE_ADDRESS, + CONFIG_DCCM_SIZE * 1024, + AUX_MPU_RDP_KW | AUX_MPU_RDP_KR), + /* Region DDR RAM */ + MPU_REGION_ENTRY("SRAM", + CONFIG_SRAM_BASE_ADDRESS, + CONFIG_SRAM_SIZE * 1024, + AUX_MPU_RDP_KW | AUX_MPU_RDP_KR | + AUX_MPU_RDP_KE | AUX_MPU_RDP_UE), + MPU_REGION_ENTRY("FLASH_0", + CONFIG_FLASH_BASE_ADDRESS, + CONFIG_FLASH_SIZE * 1024, + AUX_MPU_RDP_KR | + AUX_MPU_RDP_KE | AUX_MPU_RDP_UE), + /* Region Peripheral */ + MPU_REGION_ENTRY("PERIPHERAL", + 0xF0000000, + 64 * 1024, + AUX_MPU_RDP_KW | AUX_MPU_RDP_KR), +}; +#else /* CONFIG_USERSPACE */ +static struct arc_mpu_region mpu_regions[] = { + /* Region ICCM */ + MPU_REGION_ENTRY("ICCM", + CONFIG_ICCM_BASE_ADDRESS, + CONFIG_ICCM_SIZE * 1024, + REGION_FLASH_ATTR), + /* Region DCCM */ + MPU_REGION_ENTRY("DCCM", + CONFIG_DCCM_BASE_ADDRESS, + CONFIG_DCCM_SIZE * 1024, + REGION_RAM_ATTR), + MPU_REGION_ENTRY("FLASH_0", + CONFIG_FLASH_BASE_ADDRESS, + CONFIG_FLASH_SIZE * 1024, + REGION_FLASH_ATTR), + /* Region DDR RAM */ + MPU_REGION_ENTRY("SRAM", + CONFIG_SRAM_BASE_ADDRESS, + CONFIG_SRAM_SIZE * 1024, + REGION_ALL_ATTR), + /* Region Peripheral */ + MPU_REGION_ENTRY("PERIPHERAL", + 0xF0000000, + 64 * 1024, + REGION_IO_ATTR), +}; +#endif + +struct arc_mpu_config mpu_config = { + .num_regions = ARRAY_SIZE(mpu_regions), + .mpu_regions = mpu_regions, +}; diff --git a/boards/arc/iotdk/board.cmake b/boards/arc/iotdk/board.cmake new file mode 100644 index 00000000000..02525f205af --- /dev/null +++ b/boards/arc/iotdk/board.cmake @@ -0,0 +1,4 @@ +# TODO: can this board just use the usual openocd runner? +set(BOARD_FLASH_RUNNER em-starterkit) +set(BOARD_DEBUG_RUNNER em-starterkit) +board_finalize_runner_args(em-starterkit) diff --git a/boards/arc/iotdk/board.dtsi b/boards/arc/iotdk/board.dtsi new file mode 100644 index 00000000000..e69de29bb2d diff --git a/boards/arc/iotdk/doc/board.rst b/boards/arc/iotdk/doc/board.rst new file mode 100644 index 00000000000..eb0646ca8d3 --- /dev/null +++ b/boards/arc/iotdk/doc/board.rst @@ -0,0 +1,200 @@ +.. _iotdk: + +DesignWare(R) ARC(R) IoT Development Kit +######################################## + +Overview +******** + +The DesignWare(R) ARC(R) IoT Development Kit is a versatile platform that +includes the necessary hardware and software to accelerate software +development and debugging of sensor fusion, voice recognition, and face +detection designs. The ARC IoT Development Kit includes a silicon +implementation of the ARC Data Fusion IP Subsystem running at 144 MHz on +SMIC's 55-nm ultra-low power process, and a rich set of peripherals commonly +used in IoT designs such as USB, UART, SPI, I2C, PWM, SDIO, and ADCs. + +.. image:: iotdk_board.jpg + :width: 442px + :align: center + :alt: DesignWare(R) ARC(R)IoT Development Kit (synopsys.com) + +For details about the board, see: `ARC IoT Development Kit +(IoTDK) `__ + + +Hardware +******** + +For hardware feature details, refer to : `ARC IoT Development Kit +`__ + + +Programming and Debugging +************************* + +Required Hardware and Software +============================== + +To use Zephyr RTOS applications on the IoT Development Kit board, a few +additional pieces of hardware are required. + +* A micro USB cable provides power to the board; however, if the + board is to run standalone, the universal switching power adaptor (110-240V + AC to 5V DC), provided in the package, can be used to power the board. + +* :ref:`The Zephyr SDK ` + +* Terminal emulator software for use with the USB-UART. Suggestion: + `Putty Website`_. + +* (optional) A collection of Pmods, Arduino modules, or Mikro modules. + See `Digilent Pmod Modules`_ or develop your custom interfaces to attach + to the Pmod connector. + +Set up the ARC IoT Development Kit +================================== + +To run Zephyr application on IoT Development Kit, you need to +setup the board correctly. + +* Connect the digilent usb cable from your host to the board. + +* Connect the 5V DC power supply to your board (optional). + +Set up Zephyr Software +====================== + +Building Sample Applications +============================== + +You can try many of the sample applications or tests, but let us discuss +the one called :ref:`hello_world`. +It is found in :file:`$ZEPHYR_BASE/samples/hello_world`. + +Configuring +----------- + +You may need to write a prj_arc.conf file if the sample doesn't have one. +Next, you can use the menuconfig rule to configure the target. By specifying +``iotdk`` as the board configuration, you can select the ARC IoT Development +Kit board support for Zephyr. + +.. zephyr-app-commands:: + :board: iotdk + :zephyr-app: samples/hello_world + :goals: menuconfig + + +Building +-------- + +You can build an application in the usual way. Refer to +:ref:`build_an_application` for more details. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :board: iotdk + :zephyr-app: samples/hello_world + :maybe-skip-config: + :goals: build + +Connecting Serial Output +========================= + +In the default configuration, Zephyr's IoT Development Kit images support +serial output via the USB-UART on the board. To enable serial output: + +* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc) + +* Specify the tty driver name, for example, on Linux this may be + :file:`/dev/ttyUSB0` + +* Set the communication settings to: + + +========= ===== +Parameter Value +========= ===== +Baud: 115200 +Data: 8 bits +Parity: None +Stopbits: 1 +========= ===== + +Debugging +========== + +Using the latest version of Zephyr SDK(>=0.9), you can debug and flash IoT +Development Kit directly. + +One option is to build and debug the application using the usual +Zephyr build system commands. + +.. zephyr-app-commands:: + :board: iotdk + :app: + :goals: debug + +At this point you can do your normal debug session. Set breakpoints and then +'c' to continue into the program. + +The other option is to launch a debug server, as follows. + +.. zephyr-app-commands:: + :board: iotdk + :app: + :goals: debugserver + +Then connect to the debug server at the IoT Development Kit from a second +console, from the build directory containing the output :file:`zephyr.elf`. + +.. code-block:: console + + $ cd + $ $ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/ \ + arc-zephyr-elf/arc-zephyr-elf-gdb zephyr.elf + (gdb) target remote localhost:3333 + (gdb) load + (gdb) b main + (gdb) c + +Flashing +======== + +If you just want to download the application to the IoT Development Kit's CCM +and run, you can do so in the usual way. + +.. zephyr-app-commands:: + :board: iotdk + :app: + :goals: flash + +This command still uses openocd and gdb to load the application elf file to +IoT Development Kit, but it will load the application and immediately run. If +power is removed, the application will be lost since it wasn't written to flash. + +Most of the time you will not be flashing your program but will instead debug +it using openocd and gdb. The program can be download via the USB cable into +the code and data memories. + +When you are ready to deploy the program so that it boots up automatically on +reset or power-up, you can follow the steps to place the program on SPI-FLASH +or internal eFlash. + +For instructions on how to write your program to FLASH, refer to the +documentation on the IoT Development Kit at the `embARC website`_. + +Release Notes +************* + +References +********** + +.. _embARC website: https://www.embarc.org + +.. _Designware ARC IoT Development Kit website: `_ + +.. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules + +.. _Putty website: http://www.putty.org \ No newline at end of file diff --git a/boards/arc/iotdk/doc/iotdk_board.jpg b/boards/arc/iotdk/doc/iotdk_board.jpg new file mode 100644 index 00000000000..98406825338 Binary files /dev/null and b/boards/arc/iotdk/doc/iotdk_board.jpg differ diff --git a/boards/arc/iotdk/iotdk.dts b/boards/arc/iotdk/iotdk.dts new file mode 100644 index 00000000000..564fe944c72 --- /dev/null +++ b/boards/arc/iotdk/iotdk.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2018, Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "board.dtsi" + +/ { + model = "iotdk"; + compatible = "snps,iotdk", "snps,iotdk"; + + aliases { + uart-0 = &uart0; + }; + + chosen { + zephyr,sram = &dccm0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + }; +}; + +&uart0 { + status = "ok"; + current-speed = <115200>; +}; diff --git a/boards/arc/iotdk/iotdk.yaml b/boards/arc/iotdk/iotdk.yaml new file mode 100644 index 00000000000..9064b1e1e89 --- /dev/null +++ b/boards/arc/iotdk/iotdk.yaml @@ -0,0 +1,16 @@ +identifier: iotdk +name: IoT Development Kit +type: mcu +arch: arc +toolchain: + - zephyr + - xtools +ram: 128 +supported: + - i2c + - spi + - gpio +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/arc/iotdk/iotdk_defconfig b/boards/arc/iotdk/iotdk_defconfig new file mode 100644 index 00000000000..53064480e73 --- /dev/null +++ b/boards/arc/iotdk/iotdk_defconfig @@ -0,0 +1,13 @@ +CONFIG_ARC=y +CONFIG_SOC_ARC_IOT=y +CONFIG_BOARD_IOTDK=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_PRINTK=y +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y \ No newline at end of file diff --git a/boards/arc/iotdk/support/openocd.cfg b/boards/arc/iotdk/support/openocd.cfg new file mode 100644 index 00000000000..97af4650254 --- /dev/null +++ b/boards/arc/iotdk/support/openocd.cfg @@ -0,0 +1,52 @@ +# Copyright (C) 2018 Synopsys, Inc. +# SPDX-License-Identifier: Apache-2.0 +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program. If not, see . + +# +# Synopsys DesignWare ARC IoT Development Kit +# + +# Configure JTAG cable +# IoT DK has built-in FT2232 chip, which is similar to Digilent HS-1. +interface ftdi +ftdi_vid_pid 0x0403 0x6010 +ftdi_layout_init 0x0088 0x008b +ftdi_channel 1 + + +# EM9D requires 8 MHz. +adapter_khz 8000 + +# ARCs support only JTAG. +transport select jtag + +source [find cpu/arc/em.tcl] + +set _CHIPNAME arc-em +set _TARGETNAME $_CHIPNAME.cpu + +# IOTDK IDENTITY is 0x200444b1 +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1 + +set _coreid 0 +set _dbgbase [expr 0x00000000 | ($_coreid << 13)] + +target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \ + -coreid 0 -dbgbase $_dbgbase -endian little + +# There is no SRST, so do a software reset +$_TARGETNAME configure -event reset-assert "arc_em_reset $_TARGETNAME" + +arc_em_init_regs \ No newline at end of file diff --git a/dts/arc/arc_iot.dtsi b/dts/arc/arc_iot.dtsi new file mode 100644 index 00000000000..a891938b6b5 --- /dev/null +++ b/dts/arc/arc_iot.dtsi @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2018, Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "skeleton.dtsi" + +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "snps,arcem"; + reg = <1>; + }; + + intc: arcv2-intc { + compatible = "snps,arcv2-intc"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + iccm0: iccm@20000000 { + device_type = "memory"; + compatible = "arc,iccm"; + reg = <0x20000000 0x40000>; + }; + + dccm0: dccm@80000000 { + device_type = "memory"; + compatible = "arc,dccm"; + reg = <0x80000000 0x20000>; + }; + + + sram: memory@30000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x30000000 0x20000>; + }; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 0x40000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + + uart0: uart@80014000 { + compatible = "ns16550"; + clock-frequency = <16000000>; + reg = <0x80014000 0x100>; + label = "UART_0"; + interrupts = <86 0>; + interrupt-parent = <&intc>; + }; + + uart1: uart@80014100 { + compatible = "ns16550"; + clock-frequency = <16000000>; + reg = <0x80014100 0x100>; + label = "UART_1"; + interrupts = <87 0>; + interrupt-parent = <&intc>; + + }; + + uart2: uart@80014200 { + compatible = "ns16550"; + clock-frequency = <16000000>; + reg = <0x80014200 0x1000>; + label = "UART_2"; + interrupts = <88 0>; + interrupt-parent = <&intc>; + + }; + + uart3: uart@80014300 { + compatible = "ns16550"; + clock-frequency = <144000000>; + reg = <0x80014300 0x100>; + label = "UART_3"; + interrupts = <89 0>; + interrupt-parent = <&intc>; + + }; + + gpio8b0: gpio@80017800 { + compatible = "intel,qmsi-ss-gpio"; + reg = <0x80017800 0x100>; + interrupts = <54 1>; + interrupt-parent = <&intc>; + label = "GPIO_8B_0"; + + gpio-controller; + #gpio-cells = <2>; + }; + + gpio8b1: gpio@80017900 { + compatible = "intel,qmsi-ss-gpio"; + reg = <0x80017900 0x100>; + interrupts = <55 1>; + interrupt-parent = <&intc>; + label = "GPIO_8B_1"; + + gpio-controller; + #gpio-cells = <2>; + }; + + gpio8b2: gpio@80017a00 { + compatible = "intel,qmsi-ss-gpio"; + reg = <0x80017a00 0x100>; + interrupts = <56 1>; + interrupt-parent = <&intc>; + label = "GPIO_8B_2"; + + gpio-controller; + #gpio-cells = <2>; + }; + + gpio8b3: gpio@80017b00 { + compatible = "intel,qmsi-ss-gpio"; + reg = <0x80017b00 0x100>; + interrupts = <57 1>; + interrupt-parent = <&intc>; + label = "GPIO_8B_3"; + + gpio-controller; + #gpio-cells = <2>; + }; + + gpio4b0: gpio@80017c00 { + compatible = "intel,qmsi-ss-gpio"; + reg = <0x80017c00 0x100>; + interrupts = <19 1>; + interrupt-parent = <&intc>; + label = "GPIO_4B_0"; + + gpio-controller; + #gpio-cells = <2>; + }; + + gpio4b1: gpio@80017d00 { + compatible = "intel,qmsi-ss-gpio"; + reg = <0x80017d00 0x100>; + interrupts = <52 1>; + interrupt-parent = <&intc>; + label = "GPIO_4B_1"; + + gpio-controller; + #gpio-cells = <2>; + }; + + gpio4b2: gpio@80017e00 { + compatible = "intel,qmsi-ss-gpio"; + reg = <0x80017e00 0x100>; + interrupts = <53 1>; + interrupt-parent = <&intc>; + label = "GPIO_4B_2"; + + gpio-controller; + #gpio-cells = <2>; + }; + + + i2c0: i2c@80012000 { + compatible = "intel,qmsi-ss-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80012000 0x100>; + interrupts = <58 1>, <61 1>, <60 1>, <59 1>; + interrupt-names = "error", "stop", "tx", "rx"; + interrupt-parent = <&intc>; + label = "I2C_0"; + + status = "disabled"; + }; + + i2c1: i2c@80012100 { + compatible = "intel,qmsi-ss-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80012100 0x100>; + interrupts = <62 1>, <65 1>, <64 1>, <63 1>; + interrupt-names = "error", "stop", "tx", "rx"; + interrupt-parent = <&intc>; + label = "I2C_1"; + + status = "disabled"; + }; + + i2c2: i2c@80012200 { + compatible = "intel,qmsi-ss-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80012200 0x100>; + interrupts = <66 1>, <69 1>, <68 1>, <67 1>; + interrupt-names = "error", "stop", "tx", "rx"; + interrupt-parent = <&intc>; + label = "I2C_2"; + + status = "disabled"; + }; + + spi0: spi@80010000 { + compatible = "snps,designware-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80010000 0x100>; + interrupts = <70 2>, <71 2>, <72 2>; + interrupt-names = "err-int", "rx-avail", "tx-req"; + interrupt-parent = <&intc>; + label = "SPI_0"; + status = "disabled"; + }; + + spi1: spi@80010100 { + compatible = "snps,designware-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80010100 0x100>; + interrupts = <74 2>, <75 2>, <76 2>; + interrupt-names = "err-int", "rx-avail", "tx-req"; + interrupt-parent = <&intc>; + label = "SPI_1"; + status = "disabled"; + }; + + spi2: spi@80010200 { + compatible = "snps,designware-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80010100 0x100>; + interrupts = <78 2>, <79 2>, <80 2>; + interrupt-names = "err-int", "rx-avail", "tx-req"; + interrupt-parent = <&intc>; + label = "SPI_2"; + status = "disabled"; + }; + + }; +}; diff --git a/soc/arc/snps_arc_iot/CMakeLists.txt b/soc/arc/snps_arc_iot/CMakeLists.txt new file mode 100644 index 00000000000..4621a3cdef4 --- /dev/null +++ b/soc/arc/snps_arc_iot/CMakeLists.txt @@ -0,0 +1,13 @@ +zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_cc_option(-mcpu=${GCC_M_CPU}) +zephyr_cc_option(-mno-sdata -mdiv-rem -mswap -mnorm) +zephyr_cc_option(-mmpy-option=6 -mbarrel-shifter) +zephyr_cc_option_ifdef(CONFIG_CODE_DENSITY -mcode-density) +zephyr_cc_option_ifdef(CONFIG_FLOAT -mfpu=fpuda_all) + + +zephyr_sources( + soc.c + sysconf.c + ) diff --git a/soc/arc/snps_arc_iot/Kconfig.defconfig b/soc/arc/snps_arc_iot/Kconfig.defconfig new file mode 100644 index 00000000000..b23fc13a92b --- /dev/null +++ b/soc/arc/snps_arc_iot/Kconfig.defconfig @@ -0,0 +1,142 @@ +# +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_ARC_IOT + +config SOC + string + default "snps_arc_iot" + +config CPU_EM4_FPUS + def_bool y + +config NUM_IRQ_PRIO_LEVELS + # This processor supports 4 priority levels: + # 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs). + default 4 + +config NUM_IRQS + # must be > the highest interrupt number used + default 95 + +config RGF_NUM_BANKS + default 2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 144000000 + +config HARVARD + def_bool y + +if SERIAL + +config UART_NS16550 + def_bool y + +endif # SERIAL + +if UART_CONSOLE + +config UART_NS16550_PORT_0 + def_bool y + +endif # UART_CONSOLE + + +if GPIO + +config GPIO_QMSI_SS + def_bool y + +if GPIO_QMSI_SS + +config GPIO_QMSI_SS_0 + def_bool y + +config GPIO_QMSI_SS_1 + def_bool y + +endif # GPIO_QMSI_SS + +endif # GPIO + +if I2C + +config I2C_QMSI_SS + def_bool y + +if I2C_QMSI_SS +config I2C_SS_0 + def_bool y + +config I2C_SS_1 + def_bool y + +config I2C_SS_SDA_SETUP + default 2 + +config I2C_SS_SDA_HOLD + default 10 + +endif + +endif # I2C + + +if SPI + +config SPI_DW + def_bool y + +if SPI_DW + +config SPI_DW_FIFO_DEPTH + default 7 + +config CLOCK_CONTROL + def_bool y + +config CLOCK_CONTROL_QUARK_SE + def_bool y + +config CLOCK_CONTROL_QUARK_SE_SENSOR + def_bool y + +config SPI_0 + def_bool y + +config SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE + def_bool n + +config SPI_DW_PORT_0_CLOCK_GATE + def_bool y + +config SPI_DW_PORT_0_CLOCK_GATE_DRV_NAME + default CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME + +config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS + default 3 + +config SPI_1 + def_bool y + +config SPI_DW_PORT_1_INTERRUPT_SINGLE_LINE + def_bool n + +config SPI_DW_PORT_1_CLOCK_GATE + def_bool y + +config SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME + default CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME + +config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS + default 4 + +endif # SPI_DW +endif # SPI + +endif #ARC_IOT diff --git a/soc/arc/snps_arc_iot/Kconfig.soc b/soc/arc/snps_arc_iot/Kconfig.soc new file mode 100644 index 00000000000..676903b56bd --- /dev/null +++ b/soc/arc/snps_arc_iot/Kconfig.soc @@ -0,0 +1,9 @@ +# +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_ARC_IOT + bool "Synopsys ARC IoT SoC" diff --git a/soc/arc/snps_arc_iot/dts_fixup.h b/soc/arc/snps_arc_iot/dts_fixup.h new file mode 100644 index 00000000000..b26b8e33014 --- /dev/null +++ b/soc/arc/snps_arc_iot/dts_fixup.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* SoC level DTS fixup file */ + +/* CCM configuration */ +#define CONFIG_DCCM_BASE_ADDRESS ARC_DCCM_80000000_BASE_ADDRESS +#define CONFIG_DCCM_SIZE (ARC_DCCM_80000000_SIZE >> 10) + +#define CONFIG_ICCM_BASE_ADDRESS ARC_ICCM_20000000_BASE_ADDRESS +#define CONFIG_ICCM_SIZE (ARC_ICCM_20000000_SIZE >> 10) + +/* + * UART configuration + */ +#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR NS16550_80014000_BASE_ADDRESS +#define CONFIG_UART_NS16550_PORT_0_IRQ NS16550_80014000_IRQ_0 +#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_80014000_CLOCK_FREQUENCY +#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_80014000_CURRENT_SPEED +#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_80014000_LABEL +#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_80014000_IRQ_0_PRIORITY + +#define CONFIG_UART_NS16550_PORT_1_BASE_ADDR NS16550_80014100_BASE_ADDRESS +#define CONFIG_UART_NS16550_PORT_1_IRQ NS16550_80014100_IRQ_0 +#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ NS16550_80014100_CLOCK_FREQUENCY +#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE NS16550_80014100_CURRENT_SPEED +#define CONFIG_UART_NS16550_PORT_1_NAME NS16550_80014100_LABEL +#define CONFIG_UART_NS16550_PORT_1_IRQ_PRI NS16550_80014100_IRQ_0_PRIORITY + +#define CONFIG_UART_NS16550_PORT_2_BASE_ADDR NS16550_80014200_BASE_ADDRESS +#define CONFIG_UART_NS16550_PORT_2_IRQ NS16550_80014200_IRQ_0 +#define CONFIG_UART_NS16550_PORT_2_CLK_FREQ NS16550_80014200_CLOCK_FREQUENCY +#define CONFIG_UART_NS16550_PORT_2_BAUD_RATE NS16550_80014200_CURRENT_SPEED +#define CONFIG_UART_NS16550_PORT_2_NAME NS16550_80014200_LABEL +#define CONFIG_UART_NS16550_PORT_2_IRQ_PRI NS16550_80014200_IRQ_0_PRIORITY + + +#define CONFIG_UART_NS16550_PORT_3_BASE_ADDR NS16550_80014300_BASE_ADDRESS +#define CONFIG_UART_NS16550_PORT_3_IRQ NS16550_80014300_IRQ_0 +#define CONFIG_UART_NS16550_PORT_3_CLK_FREQ NS16550_80014300_CLOCK_FREQUENCY +#define CONFIG_UART_NS16550_PORT_3_BAUD_RATE NS16550_80014300_CURRENT_SPEED +#define CONFIG_UART_NS16550_PORT_3_NAME NS16550_80014300_LABEL +#define CONFIG_UART_NS16550_PORT_3_IRQ_PRI NS16550_80014300_IRQ_0_PRIORITY + + +/* End of SoC Level DTS fixup file */ diff --git a/soc/arc/snps_arc_iot/linker.ld b/soc/arc/snps_arc_iot/linker.ld new file mode 100644 index 00000000000..4d8a9647922 --- /dev/null +++ b/soc/arc/snps_arc_iot/linker.ld @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2018 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Linker script for the Synopsys ARC IoT Development Kit + */ + +#include + +/* + * SRAM base address and size + * + */ +#if defined(CONFIG_SRAM_BASE_ADDRESS) && (CONFIG_SRAM_SIZE > 0) +#define SRAM_START CONFIG_SRAM_BASE_ADDRESS +#define SRAM_SIZE CONFIG_SRAM_SIZE +#endif + +#if defined(CONFIG_FLASH_BASE_ADDRESS) && (CONFIG_FLASH_SIZE > 0) +#define FLASH_START CONFIG_FLASH_BASE_ADDRESS +#define FLASH_SIZE CONFIG_FLASH_SIZE +#endif + + +/* Instruction Closely Coupled Memory (ICCM) base address and size */ +#if defined(CONFIG_ICCM_BASE_ADDRESS) && (CONFIG_ICCM_SIZE > 0) +#define ICCM_START CONFIG_ICCM_BASE_ADDRESS +#define ICCM_SIZE CONFIG_ICCM_SIZE +#endif + +/* + * DCCM base address and size. DCCM is the data memory. + */ +/* Data Closely Coupled Memory (DCCM) base address and size */ +#if defined(CONFIG_DCCM_BASE_ADDRESS) && (CONFIG_DCCM_SIZE > 0) +#define DCCM_START CONFIG_DCCM_BASE_ADDRESS +#define DCCM_SIZE CONFIG_DCCM_SIZE +#endif + +#include diff --git a/soc/arc/snps_arc_iot/soc.c b/soc/arc/snps_arc_iot/soc.c new file mode 100644 index 00000000000..fe66ac7ae43 --- /dev/null +++ b/soc/arc/snps_arc_iot/soc.c @@ -0,0 +1,29 @@ + +/* + * Copyright (c) 2018 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * This module provides routines to initialize and support board-level hardware + * for the IoT Development Kit board. + * + */ +#include +#include +#include "sysconf.h" + +static int arc_iot_init(struct device *dev) +{ + ARG_UNUSED(dev); + + if (arc_iot_pll_fout_config( + CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC/1000000) < 0) { + return -1; + } + + return 0; +} + +SYS_INIT(arc_iot_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/soc/arc/snps_arc_iot/soc.h b/soc/arc/snps_arc_iot/soc.h new file mode 100644 index 00000000000..f1aca165a07 --- /dev/null +++ b/soc/arc/snps_arc_iot/soc.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2018 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Board configuration macros for EM Starter kit board + * + * This header file is used to specify and describe board-level + * aspects for the target. + */ + +#ifndef _SOC_H_ +#define _SOC_H_ + +#include + +/* default system clock */ +#define SYSCLK_DEFAULT_IOSC_HZ MHZ(16) + +/* + * UART + */ +#define UART_NS16550_ACCESS_IOPORT + + +/* ARC EM Core IRQs */ +#define IRQ_TIMER0 16 +#define IRQ_TIMER1 17 +#include "soc_irq.h" + +#define BASE_ADDR_SYSCONFIG 0xF000A000 + +#ifndef _ASMLANGUAGE + + +#include +#include + +#define ARCV2_TIMER0_INT_LVL IRQ_TIMER0 +#define ARCV2_TIMER0_INT_PRI 0 + +#define ARCV2_TIMER1_INT_LVL IRQ_TIMER1 +#define ARCV2_TIMER1_INT_PRI 1 + +#define INT_ENABLE_ARC ~(0x00000001 << 8) +#define INT_ENABLE_ARC_BIT_POS (8) + +/* + * UARTs: UART0 & UART1 & UART2 + */ +#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Default */ +#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */ +#define CONFIG_UART_NS16550_PORT_2_IRQ_FLAGS 0 /* Default */ + + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC_H_ */ diff --git a/soc/arc/snps_arc_iot/soc_irq.h b/soc/arc/snps_arc_iot/soc_irq.h new file mode 100644 index 00000000000..c3f11731b16 --- /dev/null +++ b/soc/arc/snps_arc_iot/soc_irq.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2018 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ARC_IOT_SOC_IRQ_H_ +#define _ARC_IOT_SOC_IRQ_H_ + + +#define IRQ_WATCHDOG 18 +#define IRQ_GPIO_4B0 19 +#define IRQ_DMA0_DONE 20 +#define IRQ_DMA1_DONE 21 +#define IRQ_DMA2_DONE 22 +#define IRQ_DMA3_DONE 23 +#define IRQ_DMA4_DONE 24 +#define IRQ_DMA5_DONE 25 +#define IRQ_DMA6_DONE 26 +#define IRQ_DMA7_DONE 27 +#define IRQ_DMA8_DONE 28 +#define IRQ_DMA9_DONE 29 +#define IRQ_DMA10_DONE 30 +#define IRQ_DMA11_DONE 31 +#define IRQ_DMA12_DONE 32 +#define IRQ_DMA13_DONE 33 +#define IRQ_DMA14_DONE 34 +#define IRQ_DMA15_DONE 35 +#define IRQ_DMA0_ERR 36 +#define IRQ_DMA1_ERR 37 +#define IRQ_DMA2_ERR 38 +#define IRQ_DMA3_ERR 39 +#define IRQ_DMA4_ERR 40 +#define IRQ_DMA5_ERR 41 +#define IRQ_DMA6_ERR 42 +#define IRQ_DMA7_ERR 43 +#define IRQ_DMA8_ERR 44 +#define IRQ_DMA9_ERR 45 +#define IRQ_DMA10_ERR 46 +#define IRQ_DMA11_ERR 47 +#define IRQ_DMA12_ERR 48 +#define IRQ_DMA13_ERR 49 +#define IRQ_DMA14_ERR 50 +#define IRQ_DMA15_ERR 51 + +#define IRQ_GPIO_4B1 52 +#define IRQ_GPIO_4B2 53 +#define IRQ_GPIO_8B0 54 +#define IRQ_GPIO_8B1 55 +#define IRQ_GPIO_8B2 56 +#define IRQ_GPIO_8B3 57 + +#define IRQ_I2CMST0_MST_ERR 58 +#define IRQ_I2CMST0_MST_RX_AVAIL 59 +#define IRQ_I2CMST0_MST_TX_REQ 60 +#define IRQ_I2CMST0_MST_STOP_DET 61 +#define IRQ_I2CMST1_MST_ERR 62 +#define IRQ_I2CMST1_MST_RX_AVAIL 63 +#define IRQ_I2CMST1_MST_TX_REQ 64 +#define IRQ_I2CMST1_MST_STOP_DET 65 +#define IRQ_I2CMST2_MST_ERR 66 +#define IRQ_I2CMST2_MST_RX_AVAIL 67 +#define IRQ_I2CMST2_MST_TX_REQ 68 +#define IRQ_I2CMST2_MST_STOP_DET 69 + +/* SPI */ +#define IRQ_SPIMST0_MST_ERR 70 +#define IRQ_SPIMST0_MST_RX_AVAIL 71 +#define IRQ_SPIMST0_MST_TX_REQ 72 +#define IRQ_SPIMST0_MST_IDLE 73 +#define IRQ_SPIMST1_MST_ERR 74 +#define IRQ_SPIMST1_MST_RX_AVAIL 75 +#define IRQ_SPIMST1_MST_TX_REQ 76 +#define IRQ_SPIMST1_MST_IDLE 77 +#define IRQ_SPIMST2_MST_ERR 78 +#define IRQ_SPIMST2_MST_RX_AVAIL 79 +#define IRQ_SPIMST2_MST_TX_REQ 80 +#define IRQ_SPIMST2_MST_IDLE 81 + +#define IRQ_SPISLV0_SLV_ERR 82 +#define IRQ_SPISLV0_SLV_RX_AVAIL 83 +#define IRQ_SPISLV0_SLV_TX_REQ 84 +#define IRQ_SPISLV0_SLV_IDLE 85 + +/* UART */ +#define IRQ_UART0_UART 86 +#define IRQ_UART1_UART 87 +#define IRQ_UART2_UART 88 +#define IRQ_UART3_UART 89 + +#define IRQ_EXT_WAKE_UP 90 +#define IRQ_SDIO 91 +/* I2S */ +#define IRQ_I2S_TX_EMP_0 92 +#define IRQ_I2S_TX_OR_0 93 +#define IRQ_I2S_RX_DA_0 94 +#define IRQ_I2S_RX_OR_0 95 + +#define IRQ_USB 96 +#define IRQ_ADC 97 + +#define IRQ_DW_TIMER0 98 +#define IRQ_DW_TIMER1 99 +#define IRQ_DW_TIMER2 100 +#define IRQ_DW_TIMER3 101 +#define IRQ_DW_TIMER4 102 +#define IRQ_DW_TIMER5 103 +#define IRQ_DW_RTC 104 +#define IRQ_DW_I3C 105 + +#define IRQ_RESERVED0 106 +#define IRQ_RESERVED1 107 +#define IRQ_RESERVED2 108 +#define IRQ_RESERVED3 109 +#define IRQ_RESERVED4 110 + +#endif /* _ARC_IOT_SOC_IRQ_H_ */ diff --git a/soc/arc/snps_arc_iot/sysconf.c b/soc/arc/snps_arc_iot/sysconf.c new file mode 100644 index 00000000000..69a6c9d33ae --- /dev/null +++ b/soc/arc/snps_arc_iot/sysconf.c @@ -0,0 +1,305 @@ +/* + * Copyright (c) 2018 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc.h" +#include "sysconf.h" + + +#define PLL_CLK_IN (SYSCLK_DEFAULT_IOSC_HZ / 1000000) /* PLL clock in */ + + +#define sysconf_reg_ptr ((sysconf_reg_t *)(BASE_ADDR_SYSCONFIG)) + + +typedef struct pll_conf { + uint32_t fout; + uint32_t pll; +} pll_conf_t; + +#define PLL_CONF_VAL(n, m, od) \ + (((n) << PLLCON_BIT_OFFSET_N) | \ + ((m) << (PLLCON_BIT_OFFSET_M)) | \ + ((od) << PLLCON_BIT_OFFSET_OD)) + + +/* the following configuration is based on Fin = 16 Mhz */ +static const pll_conf_t pll_configuration[] = { + {100, PLL_CONF_VAL(1, 25, 2)}, /* 100 Mhz */ + {50, PLL_CONF_VAL(1, 25, 3)}, /* 50 Mhz */ + {150, PLL_CONF_VAL(4, 75, 1)}, /* 150 Mhz */ + {75, PLL_CONF_VAL(4, 75, 2)}, /* 75 Mhz */ + {25, PLL_CONF_VAL(2, 25, 3)}, /* 25 Mhz */ + {72, PLL_CONF_VAL(8, 144, 2)}, /* 72 Mhz */ + {144, PLL_CONF_VAL(8, 144, 1)}, /* 144 Mhz */ +}; + + +/** + * PLL Fout = Fin * M/ (N *n NO) + * + * Fref = Fin / N; Fvco = Fref * M Fout = Fvco / NO + * + * N = input divider value (1, 2, 3 … 15) + * M = feedback divider value (4, 5, 6 … 16383) + * NO = output divider value (1, 2, 4, or 8) + * + * 1 Mhz <= Fref <= 50 Mhz + * 200 Mhz <= Fvco <= 400 Mhz + * + */ +void arc_iot_pll_conf_reg(uint32_t val) +{ + + sysconf_reg_ptr->CLKSEL = CLKSEL_EXT_16M; + /* 0x52000000 is not described in spec. */ + sysconf_reg_ptr->PLLCON = val | (0x52000000); + + sysconf_reg_ptr->PLLCON = val | (1 << PLLCON_BIT_OFFSET_PLLRST); + sysconf_reg_ptr->PLLCON = val & (~(1 << PLLCON_BIT_OFFSET_PLLRST)); + + while (!(sysconf_reg_ptr->PLLSTAT & (1 << PLLSTAT_BIT_OFFSET_PLLSTB))) + ; + + sysconf_reg_ptr->CLKSEL = CLKSEL_PLL; + /* from AHB_CLK_DIVIDER, not from DVFSS&PMC */ + sysconf_reg_ptr->AHBCLKDIV_SEL |= 1; + /* AHB clk divisor = 1 */ + sysconf_reg_ptr->AHBCLKDIV = 0x1; +} + +int32_t arc_iot_pll_fout_config(uint32_t freq) +{ + uint32_t i; + + if (freq == PLL_CLK_IN) { + sysconf_reg_ptr->CLKSEL = CLKSEL_EXT_16M; + } + + for (i = 0; i < ARRAY_SIZE(pll_configuration); i++) { + if (pll_configuration[i].fout == freq) { + break; + } + } + + if (i >= ARRAY_SIZE(pll_configuration)) { + return -1; + } + + /* config eflash clk, must be < 100 Mhz */ + if (freq > 100) { + arc_iot_eflash_clk_div(2); + } else { + arc_iot_eflash_clk_div(1); + } + + arc_iot_pll_conf_reg(pll_configuration[i].pll); + + return 0; +} + +void arc_iot_ahb_clk_divisor(uint8_t div) +{ + sysconf_reg_ptr->AHBCLKDIV = div; +} + +void arc_iot_ahb_clk_enable(uint8_t dev) +{ + if (dev > AHBCLKEN_BIT_SDIO) { + return; + } + + sysconf_reg_ptr->AHBCLKEN |= (1 << dev); +} + +void arc_iot_ahb_clk_disable(uint8_t dev) +{ + if (dev > AHBCLKEN_BIT_SDIO) { + return; + } + + sysconf_reg_ptr->AHBCLKEN &= (~(1 << dev)); +} + +void arc_iot_apb_clk_divisor(uint8_t div) +{ + sysconf_reg_ptr->APBCLKDIV = div; +} + +void arc_iot_apb_clk_enable(uint8_t dev) +{ + if (dev > APBCLKEN_BIT_I3C) { + return; + } + + sysconf_reg_ptr->APBCLKEN |= (1 << dev); +} + +void arc_iot_apb_clk_disable(uint8_t dev) +{ + if (dev > APBCLKEN_BIT_I3C) { + return; + } + + sysconf_reg_ptr->APBCLKEN &= (~(1 << dev)); +} + +void arc_iot_dio_clk_divisor(uint8_t div) +{ + sysconf_reg_ptr->SDIO_REFCLK_DIV; +} + + +void arc_iot_spi_master_clk_divisor(uint8_t id, uint8_t div) +{ + if (id == SPI_MASTER_0) { + sysconf_reg_ptr->SPI_MST_CLKDIV = + (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xffffff00) | div; + } else if (id == SPI_MASTER_1) { + sysconf_reg_ptr->SPI_MST_CLKDIV = + (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xffff00ff) | (div << 8); + } else if (id == SPI_MASTER_2) { + sysconf_reg_ptr->SPI_MST_CLKDIV = + (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xff00ffff) | (div << 16); + } +} + +void arc_iot_gpio8b_dbclk_div(uint8_t bank, uint8_t div) +{ + if (bank == GPIO8B_BANK0) { + sysconf_reg_ptr->GPIO8B_DBCLK_DIV = + (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0xffffff00) | div; + } else if (bank == GPIO8B_BANK1) { + sysconf_reg_ptr->GPIO8B_DBCLK_DIV = + (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0xffff00ff) | (div << 8); + } else if (bank == GPIO8B_BANK2) { + sysconf_reg_ptr->GPIO8B_DBCLK_DIV = + (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0xff00ffff) | (div << 16); + } else if (bank == GPIO8B_BANK3) { + sysconf_reg_ptr->GPIO8B_DBCLK_DIV = + (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0x00ffffff) | (div << 24); + } +} + +void arc_iot_gpio4b_dbclk_div(uint8_t bank, uint8_t div) +{ + if (bank == GPIO4B_BANK0) { + sysconf_reg_ptr->GPIO4B_DBCLK_DIV = + (sysconf_reg_ptr->GPIO4B_DBCLK_DIV & 0xffffff00) | div; + } else if (bank == GPIO4B_BANK1) { + sysconf_reg_ptr->GPIO4B_DBCLK_DIV = + (sysconf_reg_ptr->GPIO4B_DBCLK_DIV & 0xffff00ff) | (div << 8); + } else if (bank == GPIO4B_BANK2) { + sysconf_reg_ptr->GPIO4B_DBCLK_DIV = + (sysconf_reg_ptr->GPIO4B_DBCLK_DIV & 0xff00ffff) | (div << 16); + } +} + +void arc_iot_i2s_tx_clk_div(uint8_t div) +{ + sysconf_reg_ptr->I2S_TX_SCLKDIV = div; +} + +void arc_iot_i2s_rx_clk_div(uint8_t div) +{ + sysconf_reg_ptr->I2S_RX_SCLKDIV = div; +} + +void arc_iot_i2s_rx_clk_sel(uint8_t sel) +{ + sysconf_reg_ptr->I2S_RX_SCLKSEL = sel; +} + +void arc_iot_syscon_reset(void) +{ + sysconf_reg_ptr->RSTCON = 0x55AA6699; +} + +uint32_t arc_iot_is_poweron_rst(void) +{ + if (sysconf_reg_ptr->RSTSTAT & SYS_RST_SOFTWARE_ON) { + return 0; + } else { + return 1; + } +} + +void arc_iot_dvfs_clk_divisor(uint8_t level, uint8_t div) +{ + if (level == DVFS_PERF_LEVEL0) { + sysconf_reg_ptr->DVFS_CLKDIV = + (sysconf_reg_ptr->DVFS_CLKDIV & 0xffffff00) | div; + } else if (level == DVFS_PERF_LEVEL1) { + sysconf_reg_ptr->DVFS_CLKDIV = + (sysconf_reg_ptr->DVFS_CLKDIV & 0xffff00ff) | (div << 8); + } else if (level == DVFS_PERF_LEVEL2) { + sysconf_reg_ptr->DVFS_CLKDIV = + (sysconf_reg_ptr->DVFS_CLKDIV & 0xff00ffff) | (div << 16); + } else if (level == DVFS_PERF_LEVEL3) { + sysconf_reg_ptr->DVFS_CLKDIV = + (sysconf_reg_ptr->DVFS_CLKDIV & 0x00ffffff) | (div << 24); + } +} + +void arc_iot_dvfs_vdd_config(uint8_t level, uint8_t val) +{ + val &= 0xf; + + if (level == DVFS_PERF_LEVEL0) { + sysconf_reg_ptr->DVFS_VDDSET = + (sysconf_reg_ptr->DVFS_VDDSET & 0xfffffff0) | val; + } else if (level == DVFS_PERF_LEVEL1) { + sysconf_reg_ptr->DVFS_VDDSET = + (sysconf_reg_ptr->DVFS_VDDSET & 0xffffff0f) | (val << 4); + } else if (level == DVFS_PERF_LEVEL2) { + sysconf_reg_ptr->DVFS_VDDSET = + (sysconf_reg_ptr->DVFS_VDDSET & 0xfffff0ff) | (val << 8); + } else if (level == DVFS_PERF_LEVEL3) { + sysconf_reg_ptr->DVFS_CLKDIV = + (sysconf_reg_ptr->DVFS_CLKDIV & 0xffff0fff) | (val << 12); + } +} + +void arc_iot_dvfs_vwtime_config(uint8_t time) +{ + sysconf_reg_ptr->DVFS_VWTIME = time; +} + +void arc_iot_pmc_pwwtime_config(uint8_t time) +{ + sysconf_reg_ptr->PMC_PUWTIME = time; +} + +void arc_iot_uart3_clk_divisor(uint8_t div) +{ + sysconf_reg_ptr->UART3SCLK_DIV = div; +} + +void arc_iot_reset_powerdown_vector(uint32_t addr) +{ + sysconf_reg_ptr->RESET_PD_VECTOR = addr; +} + +void arc_iot_pwm_timer_pause(uint32_t id, uint32_t pause) +{ + uint32_t val = sysconf_reg_ptr->TIMER_PAUSE; + + if (id > PWM_TIMER5) { + return; + } + + if (pause) { + val |= (1 << id); + } else { + val &= (~(1 << id)); + } + + sysconf_reg_ptr->TIMER_PAUSE = val; +} + +void arc_iot_eflash_clk_div(uint8_t div) +{ + sysconf_reg_ptr->AHBCLKDIV |= (div << 8); +} \ No newline at end of file diff --git a/soc/arc/snps_arc_iot/sysconf.h b/soc/arc/snps_arc_iot/sysconf.h new file mode 100644 index 00000000000..d5a3102b92e --- /dev/null +++ b/soc/arc/snps_arc_iot/sysconf.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2018 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#ifndef _ARC_IOT_SYSCONF_H_ +#define _ARC_IOT_SYSCONF_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef struct sysconf_reg { + volatile uint32_t reserved1; /* 0x0 */ + volatile uint32_t AHBCLKDIV; /* AHB clock divisor */ + volatile uint32_t APBCLKDIV; /* APB clock divisor */ + volatile uint32_t APBCLKEN; /* APB module clock enable */ + volatile uint32_t CLKODIV; /* AHB clock output enable and divisor set */ + volatile uint32_t reserved2; /* 0x14 */ + volatile uint32_t RSTCON; /* reset contrl */ + volatile uint32_t RSTSTAT; /* reset status */ + volatile uint32_t AHBCLKDIV_SEL; /* AHB clock divisor select */ + volatile uint32_t CLKSEL; /* main clock source select */ + volatile uint32_t PLLSTAT; /* PLL status register */ + volatile uint32_t PLLCON; /* PLL control register */ + volatile uint32_t reserved3; /* 0x30 */ + volatile uint32_t AHBCLKEN; /* AHB module clock enbale */ + volatile uint32_t reserved4[2]; /* 0x38, 0x3c */ + volatile uint32_t I2S_TX_SCLKDIV; /* I2S TX SCLK divisor */ + volatile uint32_t I2S_RX_SCLKDIV; /* I2S RX SCLK divisor */ + volatile uint32_t I2S_RX_SCLKSEL; /* I2S RX SCLK source select */ + volatile uint32_t SDIO_REFCLK_DIV; /* SDIO reference clock divisor */ + volatile uint32_t GPIO4B_DBCLK_DIV; /* GPIO4B DBCLK divisor */ + volatile uint32_t IMAGE_CHK; /* Image pad status */ + volatile uint32_t PROT_RANGE; /* PROT range */ + volatile uint32_t SPI_MST_CLKDIV; /* SPI master clock divisor */ + volatile uint32_t DVFS_CLKDIV; /* DFSS main clock domain divider */ + volatile uint32_t DVFS_VDDSET; /* VDD setting */ + volatile uint32_t DVFS_VWTIME; /* VDD adjust waiting time */ + volatile uint32_t PMC_PUWTIME; /* power up waiting time */ + volatile uint32_t PMOD_MUX; /* PMOD IO mux */ + volatile uint32_t ARDUINO_MUX; /* arduino IO mux */ + volatile uint32_t USBPHY_PLL; /* USBPHY PLL */ + volatile uint32_t USBCFG; /* USB configuration */ + volatile uint32_t TIMER_PAUSE; /* PWM timer puse */ + volatile uint32_t GPIO8B_DBCLK_DIV; /* GPIO8B DBCLK divisor */ + volatile uint32_t RESET_PD_VECTOR; /* reset powerdown vector */ + volatile uint32_t UART3SCLK_DIV; /* UART3SCLK_DIV */ +} sysconf_reg_t; + +/* CLKSEL_CONST is not described in spec. */ +#define CLKSEL_CONST (0x5A690000) +#define CLKSEL_EXT_16M (0 | CLKSEL_CONST) +#define CLKSEL_PLL (1 | CLKSEL_CONST) +#define CLKSEL_EXT_32K (2 | CLKSEL_CONST) + +#define PLLCON_BIT_OFFSET_N 0 +#define PLLCON_BIT_OFFSET_M 4 +#define PLLCON_BIT_OFFSET_OD 20 +#define PLLCON_BIT_OFFSET_BP 24 +#define PLLCON_BIT_OFFSET_PLLRST 26 + + +#define PLLSTAT_BIT_OFFSET_PLLSTB 2 +#define PLLSTAT_BIT_OFFSET_PLLRDY 3 + + +#define AHBCLKEN_BIT_I2S 0 +#define AHBCLKEN_BIT_USB 1 +#define AHBCLKEN_BIT_FLASH 2 +#define AHBCLKEN_BIT_FMC 3 +#define AHBCLKEN_BIT_DVFS 4 +#define AHBCLKEN_BIT_PMC 5 +#define AHBCLKEN_BIT_BOOT_SPI 6 +#define AHBCLKEN_BIT_SDIO 7 + +#define APBCLKEN_BIT_ADC 0 +#define APBCLKEN_BIT_I2S_TX 1 +#define APBCLKEN_BIT_I2S_RX 2 +#define APBCLKEN_BIT_RTC 3 +#define APBCLKEN_BIT_PWM 4 +#define APBCLKEN_BIT_I3C 5 + + +#define SPI_MASTER_0 0 +#define SPI_MASTER_1 1 +#define SPI_MASTER_2 2 + +#define GPIO8B_BANK0 0 +#define GPIO8B_BANK1 1 +#define GPIO8B_BANK2 2 +#define GPIO8B_BANK3 3 + +#define GPIO4B_BANK0 0 +#define GPIO4B_BANK1 1 +#define GPIO4B_BANK2 2 + +/* reset caused by power on */ +#define SYS_RST_SOFTWARE_ON 0x2 + + +#define DVFS_PERF_LEVEL0 0 +#define DVFS_PERF_LEVEL1 1 +#define DVFS_PERF_LEVEL2 2 +#define DVFS_PERF_LEVEL3 3 + +/* pmode mux definition */ +#define PMOD_MUX_PMA (0x1) +#define PMOD_MUX_PMB (0x2) +#define PMOD_MUX_PMC (0x4) + +/* arduino mux definition */ +#define ARDUINO_MUX_UART (0x1) +#define ARDUINO_MUX_SPI (0x2) +#define ARDUINO_MUX_PWM0 (0x4) +#define ARDUINO_MUX_PWM1 (0x8) +#define ARDUINO_MUX_PWM2 (0x10) +#define ARDUINO_MUX_PWM3 (0x20) +#define ARDUINO_MUX_PWM4 (0x40) +#define ARDUINO_MUX_PWM5 (0x80) +#define ARDUINO_MUX_I2C (0x100) +#define ARDUINO_MUX_ADC0 (0x400) +#define ARDUINO_MUX_ADC1 (0x800) +#define ARDUINO_MUX_ADC2 (0x1000) +#define ARDUINO_MUX_ADC3 (0x2000) +#define ARDUINO_MUX_ADC4 (0x4000) +#define ARDUINO_MUX_ADC5 (0x8000) + +#define PWM_TIMER0 0 +#define PWM_TIMER1 1 +#define PWM_TIMER2 2 +#define PWM_TIMER3 3 +#define PWM_TIMER4 4 +#define PWM_TIMER5 5 + + +extern void arc_iot_pll_conf_reg(uint32_t val); +extern int32_t arc_iot_pll_fout_config(uint32_t freq); + +extern void arc_iot_ahb_clk_divisor(uint8_t div); +extern void arc_iot_ahb_clk_enable(uint8_t dev); +extern void arc_iot_ahb_clk_disable(uint8_t dev); +extern void arc_iot_sdio_clk_divisor(uint8_t div); +extern void arc_iot_spi_master_clk_divisor(uint8_t id, uint8_t div); +extern void arc_iot_gpio8b_dbclk_div(uint8_t bank, uint8_t div); +extern void arc_iot_gpio4b_dbclk_div(uint8_t bank, uint8_t div); +extern void arc_iot_i2s_tx_clk_div(uint8_t div); +extern void arc_iot_i2s_rx_clk_div(uint8_t div); +extern void arc_iot_i2s_rx_clk_sel(uint8_t sel); +extern void arc_iot_syscon_reset(void); +extern uint32_t arc_iot_is_poweron_rst(void); +extern void arc_iot_dvfs_clk_divisor(uint8_t level, uint8_t div); +extern void arc_iot_dvfs_vdd_config(uint8_t level, uint8_t val); +extern void arc_iot_dvfs_vwtime_config(uint8_t time); +extern void arc_iot_pmc_pwwtime_config(uint8_t time); +extern void arc_iot_uart3_clk_divisor(uint8_t div); +extern void arc_iot_reset_powerdown_vector(uint32_t addr); +extern void arc_iot_eflash_clk_div(uint8_t div); + +#ifdef __cplusplus +} +#endif + +#endif /* _ARC_IOT_SYSCONF_H_ */ \ No newline at end of file