arch/x86: remove CR4_PAE_DISABLE mask
This is never used. The value is incorrect, in any case. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
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@ -110,8 +110,6 @@
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/* Enable paging and write protection */
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#define CR0_PG_WP_ENABLE 0x80010000
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/* Clear the 5th bit in CR4 */
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#define CR4_PAE_DISABLE 0xFFFFFFEF
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/* Set the 5th bit in CR4 */
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#define CR4_PAE_ENABLE 0x00000020
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