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boards: nordic: Add initial support for nRF54L10 with TF-M

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This adds the nrf54l15dk/nrf54l10/cpuapp/ns board variant to
Zephyr. It allows to build applications for this target.

This is an initial support for the non secure target which allows
building and running tfm_ipc and config_build.

This is NOT full support of the non secure target in upstream
Zephyr.

There are important limitations, such as:
  - The hardware Crypto accelerator is not supported and thus the non
    secur target is NOT secure for production applications in upstream
    Zephyr.
  - The BL2 is not supported, so no DFU is supported with this support

Most of the code changes here are taken from nRF Connect SDK
in order to avoid having noups there.

Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
This commit is contained in:
Georgios Vasilakis 2025-03-26 10:22:22 +01:00 • committed by Benjamin Cabé
commit 0151535b8f
13 changed files with 225 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

4
boards/nordic/nrf54l15dk/Kconfig
View file

@ -3,7 +3,7 @@
# nRF54L15 DK board configuration
if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS
DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc)
@ -27,4 +27,4 @@ config NRF_TRUSTZONE_RAM_REGION_SIZE
This abstraction allows us to configure TrustZone without depending
on peripheral specific symbols.
endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS

4
boards/nordic/nrf54l15dk/Kconfig.defconfig
View file

@ -14,7 +14,7 @@ config ROM_START_OFFSET
endif # BOARD_NRF54L15DK_NRF54L05_CPUAPP || BOARD_NRF54L15DK_NRF54L10_CPUAPP || \
# BOARD_NRF54L15DK_NRF54L15_CPUAPP
if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS
config BT_CTLR
default BT
@ -30,4 +30,4 @@ config FLASH_LOAD_SIZE
config BUILD_WITH_TFM
default y
endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS

2
boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk
View file

@ -3,7 +3,7 @@
config BOARD_NRF54L15DK
select SOC_NRF54L05_CPUAPP if BOARD_NRF54L15DK_NRF54L05_CPUAPP
select SOC_NRF54L10_CPUAPP if BOARD_NRF54L15DK_NRF54L10_CPUAPP
select SOC_NRF54L10_CPUAPP if BOARD_NRF54L15DK_NRF54L10_CPUAPP || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS
select SOC_NRF54L15_CPUAPP if BOARD_NRF54L15DK_NRF54L15_CPUAPP || BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
select SOC_NRF54L15_CPUFLPR if BOARD_NRF54L15DK_NRF54L15_CPUFLPR || \
BOARD_NRF54L15DK_NRF54L15_CPUFLPR_XIP

2
boards/nordic/nrf54l15dk/board.cmake
View file

@ -10,7 +10,7 @@ elseif(CONFIG_SOC_NRF54L05_CPUFLPR OR CONFIG_SOC_NRF54L10_CPUFLPR)
board_runner_args(jlink "--device=RISC-V" "--speed=4000" "-if SW" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}")
endif()
if(CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS)
if(CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS OR CONFIG_BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS)
set(TFM_PUBLIC_KEY_FORMAT "full")
endif()

3
boards/nordic/nrf54l15dk/board.yml
View file

@ -5,6 +5,9 @@ board:
socs:
- name: nrf54l05
- name: nrf54l10
variants:
- name: ns
cpucluster: cpuapp
- name: nrf54l15
variants:
- name: xip

107
boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts Normal file
View file

@ -0,0 +1,107 @@
/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#define USE_NON_SECURE_ADDRESS_MAP 1
#include <nordic/nrf54l10_cpuapp.dtsi>
#include "nrf54l_05_10_15_cpuapp_common.dtsi"
/ {
compatible = "nordic,nrf54l15dk_nrf54l10-cpuapp";
model = "Nordic nRF54L15 DK nRF54L10 Application MCU";
chosen {
zephyr,code-partition = &slot0_ns_partition;
zephyr,sram = &sram0_ns;
zephyr,entropy = &psa_rng;
};
/delete-node/ rng;
psa_rng: psa-rng {
status = "okay";
};
};
/ {
/*
* Default SRAM planning when building for nRF54L10 with ARM TrustZone-M support.
* - Lowest 96 kB SRAM allocated to Secure image (sram0_s).
* - Upper 96 kB SRAM allocated to Non-Secure image (sram0_ns).
*
* nRF54L10 has 192 kB of volatile memory (SRAM) but the last 42kB are reserved for
* the FLPR MCU.
* This static layout needs to be the same with the upstream TF-M layout in the
* header flash_layout.h of the relevant platform. Any updates in the layout
* needs to happen both in the flash_layout.h and in this file at the same time.
*/
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram0_s: image_s@20000000 {
/* Secure image memory */
reg = <0x20000000 DT_SIZE_K(72)>;
};
sram0_ns: image_ns@20012000 {
/* Non-Secure image memory */
reg = <0x20012000 DT_SIZE_K(72)>;
};
};
};
&cpuapp_rram {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* nRF54L10 has 1022 kB of non volatile memory (RRAM) but the
* last 62kB are reserved for the FLPR MCU.
*
* This static layout needs to be the same with the upstream TF-M layout in the
* header flash_layout.h of the relevant platform. Any updates in the layout
* needs to happen both in the flash_layout.h and in this file at the same time.
*/
slot0_partition: partition@0 {
label = "image-0";
reg = <0x0000000 DT_SIZE_K(384)>;
};
tfm_ps_partition: partition@60000 {
label = "tfm-ps";
reg = <0x00060000 DT_SIZE_K(16)>;
};
tfm_its_partition: partition@64000 {
label = "tfm-its";
reg = <0x00064000 DT_SIZE_K(16)>;
};
tfm_otp_partition: partition@68000 {
label = "tfm-otp";
reg = <0x00068000 DT_SIZE_K(8)>;
};
slot0_ns_partition: partition@6A000 {
label = "image-0-nonsecure";
reg = <0x0006A000 DT_SIZE_K(504)>;
};
storage_partition: partition@E8000 {
label = "storage";
reg = <0x000E8000 DT_SIZE_K(32)>;
};
};
};
&uart30 {
/* Disable so that TF-M can use this UART */
status = "disabled";
};

21
boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.yaml Normal file
View file

@ -0,0 +1,21 @@
# Copyright (c) 2025 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54l15dk/nrf54l10/cpuapp/ns
name: nRF54l15-DK-nRF54l10-Application-Non-Secure
type: mcu
arch: arm
toolchain:
- gnuarmemb
- zephyr
ram: 192
flash: 1022
supported:
- adc
- gpio
- i2c
- spi
- counter
- watchdog
- adc
- i2s

36
boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns_defconfig Normal file
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@ -0,0 +1,36 @@
# Copyright (c) 2025 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
CONFIG_ARM_TRUSTZONE_M=y
# This Board implies building Non-Secure firmware
CONFIG_TRUSTED_EXECUTION_NONSECURE=y
# Don't enable the cache in the non-secure image as it is a
# secure-only peripheral on 54l
CONFIG_CACHE_MANAGEMENT=n
CONFIG_EXTERNAL_CACHE=n
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
# Start SYSCOUNTER on driver init
CONFIG_NRF_GRTC_START_SYSCOUNTER=y
# Disable TFM BL2 since it is not supported
CONFIG_TFM_BL2=n
# Support for silence logging is not supported at the moment
# Tracked by: NCSDK-31930
CONFIG_TFM_LOG_LEVEL_SILENCE=n
# The oscillators are configured as secure and cannot be configured
# from the non secure application directly. This needs to be set
# otherwise nrfx will try to configure them, resulting in a bus
# fault.
CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y

1
modules/trusted-firmware-m/Kconfig.tfm
View file

@ -26,6 +26,7 @@ config TFM_BOARD
default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf9120" if SOC_NRF9120
default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf5340_cpuapp" if SOC_NRF5340_CPUAPP
default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf54l15_cpuapp" if SOC_NRF54L15_CPUAPP
default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp" if SOC_NRF54L10_CPUAPP
help
The board name used for building TFM. Building with TFM requires that
TFM has been ported to the given board/SoC.

23
modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/CMakeLists.txt Normal file
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@ -0,0 +1,23 @@
#
# Copyright (c) 2025, Nordic Semiconductor ASA.
#
# SPDX-License-Identifier: Apache-2.0
#
set(NRF_BOARD_SELECTED True)
add_subdirectory(${Trusted\ Firmware\ M_SOURCE_DIR}/platform/ext/target/nordic_nrf/common/nrf54l10 nrf54l10)
add_subdirectory(.. common)
install(FILES ${CMAKE_CURRENT_LIST_DIR}/ns/cpuarch_ns.cmake
DESTINATION ${INSTALL_PLATFORM_NS_DIR}
RENAME cpuarch.cmake)
install(FILES config.cmake
DESTINATION ${INSTALL_PLATFORM_NS_DIR})
install(DIRECTORY ${Trusted\ Firmware\ M_SOURCE_DIR}/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests
DESTINATION ${INSTALL_PLATFORM_NS_DIR}
)

9
modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/config.cmake Normal file
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@ -0,0 +1,9 @@
#
# Copyright (c) 2025, Nordic Semiconductor ASA.
#
# SPDX-License-Identifier: Apache-2.0
#
set(NRF_SOC_VARIANT nrf54l10 CACHE STRING "nRF SoC Variant")
include(${PLATFORM_PATH}/common/nrf54l10/config.cmake)

9
modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/cpuarch.cmake Normal file
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@ -0,0 +1,9 @@
#
# Copyright (c) 2025, Nordic Semiconductor ASA.
#
# SPDX-License-Identifier: Apache-2.0
#
set(PLATFORM_PATH platform/ext/target/nordic_nrf)
include(${PLATFORM_PATH}/common/nrf54l10/cpuarch.cmake)

10
modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/ns/cpuarch_ns.cmake Normal file
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@ -0,0 +1,10 @@
#
# Copyright (c) 2025, Nordic Semiconductor ASA.
#
# SPDX-License-Identifier: Apache-2.0
#
set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR})
set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR})
include(${CMAKE_CURRENT_LIST_DIR}/common/nrf54l10/cpuarch.cmake)