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arm64: gic: Enable access to ICC_* registers

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Thi GICv3 driver is configuring the controller accessing the system
registers ICC_*. To be able to do that without trapping we have to
explicitly set at boot in EL3 the value of the ICC_SRE_EL3 register that
is architecturally set to UNKNOWN value on warm reset.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione 2021-04-12 20:30:38 +02:00 • committed by Carles Cufí
commit 013c8273ca
1 changed files with 7 additions and 0 deletions
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7
arch/arm64/core/reset.c
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@ -87,6 +87,13 @@ void z_arm64_el3_init(void)
SCR_SMD_BIT); /* Do not trap SMC */
write_scr_el3(reg);
#if defined(CONFIG_GIC_V3)
reg = read_sysreg(ICC_SRE_EL3);
reg = (ICC_SRE_ELx_SRE_BIT | /* System register interface is used */
ICC_SRE_EL3_EN_BIT); /* Enables lower Exception level access to ICC_SRE_EL1 */
write_sysreg(reg, ICC_SRE_EL3);
#endif
z_arm64_el3_plat_init();
isb();