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driver: reset: npcx: add driver support for reset controller

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Nuvoton NPCX chips have reset registers which allow to reset the
peripheral hardware modules. This commit adds the support by
implementing the reset driver. Note that only the reset_line_toggle API
is supported because of the nature of the reset controller's design.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commit is contained in:
Jun Lin 2024-04-01 10:34:25 +08:00 • committed by Alberto Escolar
commit 011b730b4c
13 changed files with 458 additions and 0 deletions
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8
soc/nuvoton/npcx/common/reg/reg_def.h
View file

@ -1756,4 +1756,12 @@ struct spip_reg {
#define NPCX_SPIP_STAT_BSY 0
#define NPCX_SPIP_STAT_RBF 1
/* Software-triggered Pheripheral Reset Controller Register */
struct swrst_reg {
/* 0x000: Software Reset Trigger */
volatile uint16_t SWRST_TRG;
volatile uint8_t reserved1[2];
volatile uint32_t SWRST_CTL[4];
};
#endif /* _NUVOTON_NPCX_REG_DEF_H */

8
soc/nuvoton/npcx/common/registers.c
View file

@ -189,3 +189,11 @@ NPCX_REG_OFFSET_CHECK(kbs_reg, KBS_BUF_INDX, 0x00a);
/* SPIP register structure check */
NPCX_REG_SIZE_CHECK(spip_reg, 0x006);
NPCX_REG_OFFSET_CHECK(spip_reg, SPIP_CTL1, 0x002);
/* SWRST register structure check */
NPCX_REG_SIZE_CHECK(swrst_reg, 0x014);
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_TRG, 0x000);
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[0], 0x004);
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[1], 0x008);
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[2], 0x00c);
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[3], 0x010);