x86: add Quark D2000 Interrupt Controller (MVIC)
This module is based on the standard Local APIC and IO APIC source modules. This modules combines these modules into one source module that exports the same APIs defined by the Local APIC and IO APIC header modules. These routine have been adapted for the Quark D2000 Interrupt Controller which has a cutdown implementation of the Local APIC & IO APIC register sets. Change-Id: Ic80aa78918483663d76054ebadefa08d8a3f188a Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif
parent
b0b936b51c
commit
00c4d32d42
6 changed files with 594 additions and 4 deletions
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@ -37,7 +37,7 @@ config LOAPIC_DEBUG
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config LOAPIC_BASE_ADDRESS
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hex "Local APIC Base Address"
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default 0xFEE00000
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depends on LOAPIC
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depends on LOAPIC || MVIC
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help
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This option specifies the base address of the Local APIC device.
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@ -59,7 +59,7 @@ config IOAPIC_DEBUG
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config IOAPIC_BASE_ADDRESS
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hex "IO-APIC Base Address"
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default 0xFEC00000
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depends on IOAPIC
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depends on IOAPIC || MVIC
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help
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This option specifies the base address of the IO-APIC device.
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@ -74,6 +74,17 @@ config IOAPIC_NUM_RTES
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most efficient usage of memory, it should match the number of IRQ lines
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needed by devices connected to the IO-APIC.
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config MVIC
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bool "Intel Quark D2000 Interrupt Controller (MVIC)"
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default n
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depends on X86_32
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help
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The MVIC (Intel Quark microcontroller D2000 Interrupt Controller) is
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configured by default to support 32 external interrupt lines. Unlike the
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traditional IA LAPIC/IOAPIC, the interrupt vectors in MVIC are fixed and
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not programmable. In addition, the priorities of these interrupt
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lines are also fixed.
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config ARCV2_INTERRUPT_UNIT
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bool "ARCv2 Interrupt Unit"
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default y
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@ -1,6 +1,7 @@
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obj-${CONFIG_PIC_DISABLE} = i8259.o
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obj-$(CONFIG_LOAPIC) += system_apic.o
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obj-$(CONFIG_LOAPIC)$(CONFIG_MVIC) += system_apic.o
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obj-$(CONFIG_MVIC) += mvic.o
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obj-$(CONFIG_LOAPIC) += loapic_intr.o
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obj-$(CONFIG_IOAPIC) += ioapic_intr.o
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525
drivers/interrupt_controller/mvic.c
Normal file
525
drivers/interrupt_controller/mvic.c
Normal file
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@ -0,0 +1,525 @@
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/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Quark D2000 Interrupt Controller (MVIC)
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*
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* This module is based on the standard Local APIC and IO APIC source modules.
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* This modules combines these modules into one source module that exports the
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* same APIs defined by the Local APIC and IO APIC header modules. These
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* routine have been adapted for the Quark D2000 Interrupt Controller which has
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* a cutdown implementation of the Local APIC & IO APIC register sets.
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*
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* The MVIC (Quark D2000 Interrupt Controller) is configured by default
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* to support 32 external interrupt lines.
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* Unlike the traditional IA LAPIC/IOAPIC, the interrupt vectors in MVIC are fixed
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* and not programmable.
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* The larger the vector number, the higher the priority of the interrupt.
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* Higher priority interrupts preempt lower priority interrupts.
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* Lower priority interrupts do not preempt higher priority interrupts.
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* The MVIC holds the lower priority interrupts pending until the interrupt
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* service routine for the higher priority interrupt writes to the End of
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* Interrupt (EOI) register.
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* After an EOI write, the MVIC asserts the next highest pending interrupt.
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*
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* INCLUDE FILES: ioapic.h loapic.h
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*
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*/
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/* includes */
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#include <nanokernel.h>
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#include <arch/cpu.h>
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#include <misc/__assert.h>
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#include "board.h"
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#include <toolchain.h>
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#include <sections.h>
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#include <drivers/ioapic.h> /* IO APIC public API declarations. */
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#include <drivers/loapic.h> /* Local APIC public API declarations.*/
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/* defines */
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/* IO APIC direct register offsets */
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#define IOAPIC_IND 0x00 /* Index Register - MVIC IOREGSEL register */
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#define IOAPIC_DATA 0x10 /* IO window (data) - pc.h */
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/* MVIC IOREGSEL register usage defines */
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#define MVIC_LOW_NIBBLE_MASK 0x07
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#define MVIC_HIGH_NIBBLE_MASK 0x18
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/* MVIC Local APIC Vector Table Bits */
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#define LOAPIC_VECTOR 0x000000ff /* vectorNo */
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/* MVIC Local APIC Spurious-Interrupt Register Bits */
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#define LOAPIC_ENABLE 0x100 /* APIC Enabled */
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/* forward declarations */
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static void _mvic_rte_set(unsigned int irq, uint32_t value);
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static uint32_t _mvic_rte_get(unsigned int irq);
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static void _mvic_rte_update(unsigned int irq, uint32_t value,
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uint32_t mask);
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/*
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* The functions irq_enable() and irq_disable() are implemented
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* in the platforms that incorporate this interrupt controller driver due to the
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* IRQ virtualization imposed by the platform.
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*/
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/**
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*
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* @brief initialize the MVIC IO APIC and local APIC register sets.
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*
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* This routine initializes the Quark D2000 Interrupt Controller (MVIC).
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* This routine replaces the standard Local APIC / IO APIC init routines.
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*
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* @returns: N/A
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*/
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int _mvic_init(struct device *unused)
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{
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ARG_UNUSED(unused);
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int32_t ix; /* Interrupt line register index */
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uint32_t rteValue; /* value to copy into interrupt line register */
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/*
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* The platform must define the CONFIG_IOAPIC_NUM_RTES macro to indicate the number
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* of redirection table entries supported by the IOAPIC on the board.
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*
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* By default mask all interrupt lines and set default sensitivity to edge.
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*
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*/
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rteValue = IOAPIC_EDGE | IOAPIC_INT_MASK;
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for (ix = 0; ix < CONFIG_IOAPIC_NUM_RTES; ix++) {
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_mvic_rte_set(ix, rteValue);
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}
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/* enable the MVIC Local APIC */
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_loapic_enable();
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/* reset the TPR, and TIMER_ICR */
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*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TPR) = (int)0x0;
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*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER_ICR) = (int)0x0;
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/* program Local Vector Table for the Virtual Wire Mode */
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/* lock the MVIC timer interrupt */
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*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER) = LOAPIC_LVT_MASKED;
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/* discard a pending interrupt if any */
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*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI) = 0;
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return 0;
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}
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/**
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*
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* @brief Send EOI (End Of Interrupt) signal to IO APIC
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*
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* This routine sends an EOI signal to the IO APIC's interrupting source.
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*
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* All line interrupts on Quark D2000 are EOI'ed with local APIC EOI register.
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*
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* @param irq INT number to send EOI
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*
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* @returns: N/A
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*/
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void _ioapic_eoi(unsigned int irq)
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{
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_loapic_eoi();
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}
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/**
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*
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* @brief Get EOI (End Of Interrupt) information
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*
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* This routine returns EOI signalling information for a specific IRQ.
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*
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* @param irq INTIN number of interest
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* @param argRequired ptr to "argument required" result area
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* @param arg ptr to "argument value" result area
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*
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* @returns: address of routine to be called to signal EOI;
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* as a side effect, also passes back indication if routine requires
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* an interrupt vector argument and what the argument value should be
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*/
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void *_ioapic_eoi_get(unsigned int irq, char *argRequired, void **arg)
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{
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/* indicate that an argument to the EOI handler is required */
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*argRequired = 1;
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/*
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* The parameter to the ioApicIntEoi() routine is the vector programmed
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* into the redirection table. The platform _SysIntVecAlloc() routine
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* must invoke _IoApicIntEoiGet() after _IoApicRedVecSet() to ensure the
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* redirection table contains the desired interrupt vector.
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*
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* Vectors fixed on this CPU Arch, no memory location on this CPU
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* arch with this information.
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*/
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*arg = NULL;
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/* lo eoi always used on this CPU arch. */
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return _loapic_eoi;
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}
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/**
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*
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* @brief Enable a specified APIC interrupt input line
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*
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* This routine enables a specified APIC interrupt input line.
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*
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* @param irq INTIN number to enable
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*
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* @returns: N/A
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*/
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void _ioapic_irq_enable(unsigned int irq)
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{
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_mvic_rte_update(irq, 0, IOAPIC_INT_MASK);
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}
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/**
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*
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* @brief disable a specified APIC interrupt input line
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*
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* This routine disables a specified APIC interrupt input line.
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*
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* @param irq INTIN number to disable
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*
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* @returns: N/A
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*/
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void _ioapic_irq_disable(unsigned int irq)
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{
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_mvic_rte_update(irq, IOAPIC_INT_MASK, IOAPIC_INT_MASK);
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}
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/**
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*
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* @brief Programs Rte interrupt line register.
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*
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* Always mask interrupt as part of programming like standard IOAPIC
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* version of this routine.
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* Vector is fixed by this HW and is unused.
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* Or in flags for trigger bit.
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*
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* @param irq Virtualized IRQ
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* @param vector Vector Number
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* @param flags Interrupt flags
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*
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* @returns: N/A
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*/
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void _ioapic_irq_set(unsigned int irq, unsigned int vector, uint32_t flags)
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{
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uint32_t rteValue; /* value to copy into Rte register */
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ARG_UNUSED(vector);
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rteValue = IOAPIC_INT_MASK | flags;
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_mvic_rte_set(irq, rteValue);
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}
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/**
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*
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* @brief program interrupt vector for specified irq
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*
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* Fixed vector on this HW. Nothing to do.
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*
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* @param irq Interrupt number
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* @param vector Vector number
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*
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* @returns: N/A
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*/
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void _ioapic_int_vec_set(unsigned int irq, unsigned int vector)
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{
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}
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/**
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*
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* @brief Enable the MVIC Local APIC
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*
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* This routine enables the MVIC Local APIC.
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*
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* @returns: N/A
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*/
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void _loapic_enable(void)
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{
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int32_t oldLevel = irq_lock(); /* LOCK INTERRUPTS */
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*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) |= LOAPIC_ENABLE;
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irq_unlock(oldLevel); /* UNLOCK INTERRUPTS */
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}
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/**
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*
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* @brief Disable the MVIC Local APIC.
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*
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* This routine disables the MVIC Local APIC.
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*
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* @returns: N/A
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*/
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void _loapic_disable(void)
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{
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int32_t oldLevel = irq_lock(); /* LOCK INTERRUPTS */
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*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_SVR) &= ~LOAPIC_ENABLE;
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irq_unlock(oldLevel); /* UNLOCK INTERRUPTS */
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}
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/**
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*
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* @brief Set the vector field in the specified RTE
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*
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* This routine is utilized by the platform-provided routined _SysIntVecAllocate()
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* which in turn is provided to support the irq_connect() API. Once
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* a vector has been allocated, this routine is invoked to update the LVT
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* entry associated with <irq> with the vector.
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*
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* @param irq IRQ number of the interrupt
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* @param vector vector to copy into the LVT
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*
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* @returns N/A
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*/
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void _loapic_int_vec_set(unsigned int irq, unsigned int vector)
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{
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volatile int *pLvt; /* pointer to local vector table */
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int32_t oldLevel; /* previous interrupt lock level */
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/*
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* irq is actually an index to local APIC LVT register.
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* ASSERT if out of range for MVIC implementation.
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*/
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__ASSERT_NO_MSG(irq < LOAPIC_IRQ_COUNT);
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/*
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* The following mappings are used:
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*
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* LVT0 -> LOAPIC_TIMER
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*
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* It's assumed that LVTs are spaced by LOAPIC_LVT_REG_SPACING bytes
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*/
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pLvt = (volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER +
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(irq * LOAPIC_LVT_REG_SPACING));
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/* update the 'vector' bits in the LVT */
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oldLevel = irq_lock();
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*pLvt = (*pLvt & ~LOAPIC_VECTOR) | vector;
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irq_unlock(oldLevel);
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}
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/**
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*
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* @brief enable an individual LOAPIC interrupt (IRQ)
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*
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* This routine clears the interrupt mask bit in the LVT for the specified IRQ
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*
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* @param irq IRQ number of the interrupt
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*
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* @returns N/A
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*/
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void _loapic_irq_enable(unsigned int irq)
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{
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volatile int *pLvt; /* pointer to local vector table */
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int32_t oldLevel; /* previous interrupt lock level */
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/*
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* irq is actually an index to local APIC LVT register.
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* ASSERT if out of range for MVIC implementation.
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*/
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__ASSERT_NO_MSG(irq < LOAPIC_IRQ_COUNT);
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/*
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* See the comments in _LoApicLvtVecSet() regarding IRQ to LVT mappings
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* and ths assumption concerning LVT spacing.
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*/
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pLvt = (volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER +
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(irq * LOAPIC_LVT_REG_SPACING));
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/* clear the mask bit in the LVT */
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oldLevel = irq_lock();
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*pLvt = *pLvt & ~LOAPIC_LVT_MASKED;
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irq_unlock(oldLevel);
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}
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/**
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*
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* @brief disable an individual LOAPIC interrupt (IRQ)
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*
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* This routine clears the interrupt mask bit in the LVT for the specified IRQ
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*
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* @param irq IRQ number of the interrupt
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*
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* @returns N/A
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*/
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void _loapic_irq_disable(unsigned int irq)
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{
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volatile int *pLvt; /* pointer to local vector table */
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int32_t oldLevel; /* previous interrupt lock level */
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/*
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* irq is actually an index to local APIC LVT register.
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* ASSERT if out of range for MVIC implementation.
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*/
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__ASSERT_NO_MSG(irq < LOAPIC_IRQ_COUNT);
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/*
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* See the comments in _LoApicLvtVecSet() regarding IRQ to LVT mappings
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* and ths assumption concerning LVT spacing.
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*/
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pLvt = (volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER +
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(irq * LOAPIC_LVT_REG_SPACING));
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/* set the mask bit in the LVT */
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oldLevel = irq_lock();
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*pLvt = *pLvt | LOAPIC_LVT_MASKED;
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irq_unlock(oldLevel);
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}
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/**
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*
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* @brief read a 32 bit MVIC IO APIC register
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*
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* @param irq INTIN number
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*
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* @returns register value
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*/
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static uint32_t _mvic_rte_get(unsigned int irq)
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{
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uint32_t value; /* value */
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int key; /* interrupt lock level */
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volatile unsigned int *rte;
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volatile unsigned int *index;
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unsigned int low_nibble;
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unsigned int high_nibble;
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index = (unsigned int *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_IND);
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rte = (unsigned int *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA);
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/* Set index in the IOREGSEL */
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__ASSERT(irq < CONFIG_IOAPIC_NUM_RTES, "INVL");
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low_nibble = ((irq & MVIC_LOW_NIBBLE_MASK) << 0x1);
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high_nibble = ((irq & MVIC_HIGH_NIBBLE_MASK) << 0x2);
|
||||
|
||||
/* lock interrupts to ensure indirect addressing works "atomically" */
|
||||
|
||||
key = irq_lock();
|
||||
|
||||
*(index) = high_nibble | low_nibble;
|
||||
value = *(rte);
|
||||
|
||||
irq_unlock(key);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief write to 32 bit MVIC IO APIC register
|
||||
*
|
||||
* @param irq INTIN number
|
||||
* @param value value to be written
|
||||
*
|
||||
* @returns N/A
|
||||
*/
|
||||
static void _mvic_rte_set(unsigned int irq, uint32_t value)
|
||||
{
|
||||
int key; /* interrupt lock level */
|
||||
volatile unsigned int *rte;
|
||||
volatile unsigned int *index;
|
||||
unsigned int low_nibble;
|
||||
unsigned int high_nibble;
|
||||
|
||||
index = (unsigned int *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_IND);
|
||||
rte = (unsigned int *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA);
|
||||
|
||||
/* Set index in the IOREGSEL */
|
||||
__ASSERT(irq < CONFIG_IOAPIC_NUM_RTES, "INVL");
|
||||
|
||||
low_nibble = ((irq & MVIC_LOW_NIBBLE_MASK) << 0x1);
|
||||
high_nibble = ((irq & MVIC_HIGH_NIBBLE_MASK) << 0x2);
|
||||
|
||||
/* lock interrupts to ensure indirect addressing works "atomically" */
|
||||
|
||||
key = irq_lock();
|
||||
|
||||
*(index) = high_nibble | low_nibble;
|
||||
*(rte) = (value & IOAPIC_LO32_RTE_SUPPORTED_MASK);
|
||||
|
||||
irq_unlock(key);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief modify interrupt line register.
|
||||
*
|
||||
* @param irq INTIN number
|
||||
* @param value value to be written
|
||||
* @param mask of bits to be modified
|
||||
*
|
||||
* @returns N/A
|
||||
*/
|
||||
static void _mvic_rte_update(unsigned int irq, uint32_t value, uint32_t mask)
|
||||
{
|
||||
_mvic_rte_set(irq, (_mvic_rte_get(irq) & ~mask) | (value & mask));
|
||||
}
|
||||
|
||||
void loapic_int_vec_trigger(unsigned int vector)
|
||||
{
|
||||
uint32_t icr_cmd;
|
||||
|
||||
/*
|
||||
* Bit 14 : level ASSERT (1)
|
||||
* Bit 18-19: Destination shorthand SELF (01)
|
||||
* Bit 15 : trigger mode EDGE (0)
|
||||
*
|
||||
* Destination mode ignored
|
||||
*/
|
||||
icr_cmd = vector | (1 << 14) | (1 << 18);
|
||||
|
||||
*(volatile int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_ICRLO) = icr_cmd;
|
||||
}
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue