dts: set the riscv,isa property for virt-based targets

This commit makes the devicetrees of the targets that are based on the QEMU
`virt` machine more consistent with the rest of the RISC-V targets in
Zephyr by:
* adding the `riscv,isa` property
* adding a compatible string which uniquely identifies the `virt` core

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>

dts/bindings/cpu/qemu,riscv-virt.yaml

@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: QEMU RISC-V virt machine CPU node
+
+compatible: "qemu,riscv-virt"
+
+include: riscv,cpus.yaml