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boards: mimxrt1010_evk: Fix drive strength in pinmux

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MCUXpresso SDK sets the drive strength of LPUART and LPI2C pins to 4 for
this SOC, versus 6 for most other RT10xx boards. Update the pinmux.c
file for mimxrt1010_evk to reflect this.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2021-10-11 14:54:56 -05:00 • committed by Christopher Friedt
commit 0076a3b5da
1 changed files with 8 additions and 4 deletions
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12
boards/arm/mimxrt1010_evk/pinmux.c
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@ -36,6 +36,10 @@ static int mimxrt1010_evk_init(const struct device *dev)
IOMUXC_SW_PAD_CTL_PAD_DSE(4)); IOMUXC_SW_PAD_CTL_PAD_DSE(4));
#endif #endif
/* MCUX SDK sets the drive strength of pins on RT1010 to 4 by default,
* hence the difference between the drive strength selected here and in other
* board pinmux files
*/
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) && CONFIG_SERIAL #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) && CONFIG_SERIAL
/* LPUART1 TX/RX */ /* LPUART1 TX/RX */
IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0); IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0);
@ -44,12 +48,12 @@ static int mimxrt1010_evk_init(const struct device *dev)
IOMUXC_SetPinConfig(IOMUXC_GPIO_09_LPUART1_RXD, IOMUXC_SetPinConfig(IOMUXC_GPIO_09_LPUART1_RXD,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6)); IOMUXC_SW_PAD_CTL_PAD_DSE(4));
IOMUXC_SetPinConfig(IOMUXC_GPIO_10_LPUART1_TXD, IOMUXC_SetPinConfig(IOMUXC_GPIO_10_LPUART1_TXD,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6)); IOMUXC_SW_PAD_CTL_PAD_DSE(4));
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay) && CONFIG_I2C #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay) && CONFIG_I2C
@ -62,14 +66,14 @@ static int mimxrt1010_evk_init(const struct device *dev)
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6)); IOMUXC_SW_PAD_CTL_PAD_DSE(4));
IOMUXC_SetPinConfig(IOMUXC_GPIO_01_LPI2C1_SDA, IOMUXC_SetPinConfig(IOMUXC_GPIO_01_LPI2C1_SDA,
IOMUXC_SW_PAD_CTL_PAD_PUS(3) | IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6)); IOMUXC_SW_PAD_CTL_PAD_DSE(4));
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay) && CONFIG_SPI #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay) && CONFIG_SPI