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soc: arc: Increase cpu frequency for nsim_hs_smp

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0.5 Mhz with 100 ticks per sec leaves 5000 cycles per tick,
which broke some tests that assumed more work within 1 tick.
Set to 1 Mhz: balance multi-core simulation speed and tick duration.

Fixes #27943

Signed-off-by: Ruud Derwig <Ruud.Derwig@synopsys.com>
This commit is contained in:
Ruud Derwig 2020-09-08 11:49:31 +02:00 • committed by Maureen Helm
commit 0076313bcb
1 changed files with 2 additions and 1 deletions
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soc/arc/snps_nsim/Kconfig.defconfig.hs_smp
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@ -16,7 +16,8 @@ config RGF_NUM_BANKS
default 2 default 2
config SYS_CLOCK_HW_CYCLES_PER_SEC config SYS_CLOCK_HW_CYCLES_PER_SEC
default 500000 # SMP simulation is slower than single core, 1 Mhz seems reasonable match with wallclock
default 1000000
config HARVARD config HARVARD
default y default y