388 lines
12 KiB
Text
388 lines
12 KiB
Text
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# Kconfig.ia32 - IA32-specific X86 subarchitecture options
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#
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# Copyright (c) 2019 Intel Corp.
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# SPDX-License-Identifier: Apache-2.0
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#
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if !X86_LONGMODE
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config NESTED_INTERRUPTS
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bool "Enable nested interrupts"
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default y
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help
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This option enables support for nested interrupts.
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config EXCEPTION_DEBUG
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bool "Unhandled exception debugging"
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default y
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depends on PRINTK
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help
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Install handlers for various CPU exception/trap vectors to
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make debugging them easier, at a small expense in code size.
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This prints out the specific exception vector and any associated
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error codes.
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menu "Memory Layout Options"
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config IDT_NUM_VECTORS
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int "Number of IDT vectors"
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default 256
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range 32 256
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help
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This option specifies the number of interrupt vector entries in the
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Interrupt Descriptor Table (IDT). By default all 256 vectors are
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supported in an IDT requiring 2048 bytes of memory.
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config MAX_IRQ_LINES
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int "Number of IRQ lines"
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default 128
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range 0 256
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help
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This option specifies the number of IRQ lines in the system.
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It can be tuned to save some bytes in ROM, as it determines the
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size of the _irq_to_interrupt_vector_table, which is used at runtime
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to program to the PIC the association between vectors and
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interrupts.
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config SET_GDT
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bool "Setup GDT as part of boot process"
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default y
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help
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This option sets up the GDT as part of the boot process. However,
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this may conflict with some security scenarios where the GDT is
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already appropriately set by an earlier bootloader stage, in which
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case this should be disabled. If disabled, the global _gdt pointer
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will not be available.
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config GDT_DYNAMIC
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bool "Store GDT in RAM so that it can be modified"
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depends on SET_GDT
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help
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This option stores the GDT in RAM instead of ROM, so that it may
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be modified at runtime at the expense of some memory.
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endmenu
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config DISABLE_SSBD
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bool "Disable Speculative Store Bypass"
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depends on USERSPACE
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default y if !X86_NO_SPECTRE_V4
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help
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This option will disable Speculative Store Bypass in order to
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mitigate against certain kinds of side channel attacks. Quoting
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the "Speculative Execution Side Channels" document, version 2.0:
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When SSBD is set, loads will not execute speculatively
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until the addresses of all older stores are known. This
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ensure s that a load does not speculatively consume stale
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data values due to bypassing an older store on the same
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logical processor.
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If enabled, this applies to all threads in the system.
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Even if enabled, will have no effect on CPUs that do not
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require this feature.
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config ENABLE_EXTENDED_IBRS
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bool "Enable Extended IBRS"
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depends on USERSPACE
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default y if !X86_NO_SPECTRE_V2
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help
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This option will enable the Extended Indirect Branch Restricted
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Speculation 'always on' feature. This mitigates Indirect Branch
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Control vulnerabilities (aka Spectre V2).
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config X86_RETPOLINE
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bool "Build with retpolines enabled in x86 assembly code"
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depends on USERSPACE
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help
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This is recommended on platforms with speculative executions, to
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protect against branch target injection (AKA Spectre-V2). Full
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description of how retpolines work can be found here[1].
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[1] https://support.google.com/faqs/answer/7625886
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config X86_BOUNDS_CHECK_BYPASS_MITIGATION
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bool
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depends on USERSPACE
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default y if !X86_NO_SPECTRE_V1
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select BOUNDS_CHECK_BYPASS_MITIGATION
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help
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Hidden config to select arch-independent option to enable
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Spectre V1 mitigations by default if the CPU is not known
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to be immune to it.
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menu "Processor Capabilities"
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config X86_IAMCU
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bool "IAMCU calling convention"
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help
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The IAMCU calling convention changes the X86 C calling convention to
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pass some arguments via registers allowing for code size and performance
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improvements. Great care needs to be taken if you have assembly code
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that will be called from C or C code called from assembly code, the
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assembly code will need to be updated to conform to the new calling
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convention. If in doubt say N
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config X86_MMU
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bool "Enable Memory Management Unit"
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select MEMORY_PROTECTION
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help
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This options enables the memory management unit present in x86
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and creates a set of page tables at build time. Requires an MMU
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which supports PAE page tables.
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config X86_NO_MELTDOWN
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Meltdown CPU vulnerability,
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as described in CVE-2017-5754.
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config X86_NO_SPECTRE_V1
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Spectre V1, V1.1, and V1.2
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CPU vulnerabilities as described in CVE-2017-5753 and CVE-2018-3693.
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config X86_NO_SPECTRE_V2
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Spectre V2 CPU
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vulnerability, as described in CVE-2017-5715.
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config X86_NO_SPECTRE_V4
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Spectre V4 CPU
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vulnerability, as described in CVE-2018-3639.
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config X86_NO_LAZY_FP
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate
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that a particular SOC is not vulnerable to the Lazy FP CPU
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vulnerability, as described in CVE-2018-3665.
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config X86_NO_SPECULATIVE_VULNERABILITIES
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bool
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select X86_NO_MELTDOWN
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select X86_NO_SPECTRE_V1
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select X86_NO_SPECTRE_V2
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select X86_NO_SPECTRE_V4
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select X86_NO_LAZY_FP
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC does not perform any kind of speculative execution,
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or is a newer chip which is immune to the class of vulnerabilities
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which exploit speculative execution side channel attacks.
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config X86_ENABLE_TSS
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bool
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help
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This hidden option enables defining a Task State Segment (TSS) for
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kernel execution. This is needed to handle double-faults or
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do privilege elevation. It also defines a special TSS and handler
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for correctly handling double-fault exceptions, instead of just
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letting the system triple-fault and reset.
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config X86_STACK_PROTECTION
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bool
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default y if HW_STACK_PROTECTION
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select SET_GDT
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select GDT_DYNAMIC
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select X86_ENABLE_TSS
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help
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This option leverages the MMU to cause a system fatal error if the
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bounds of the current process stack are overflowed. This is done
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by preceding all stack areas with a 4K guard page.
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config X86_USERSPACE
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bool
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default y if USERSPACE
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select THREAD_STACK_INFO
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select SET_GDT
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select GDT_DYNAMIC
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select X86_ENABLE_TSS
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help
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This option enables APIs to drop a thread's privileges down to ring 3,
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supporting user-level threads that are protected from each other and
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from crashing the kernel.
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config X86_KPTI
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bool "Enable kernel page table isolation"
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default y
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depends on USERSPACE
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depends on !X86_NO_MELTDOWN
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help
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Implements kernel page table isolation to mitigate Meltdown exploits
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to read Kernel RAM. Incurs a significant performance cost for
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user thread interrupts and system calls, and significant footprint
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increase for additional page tables and trampoline stacks.
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menu "Architecture Floating Point Options"
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depends on CPU_HAS_FPU
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config SSE
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bool "SSE registers"
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depends on FLOAT
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help
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This option enables the use of SSE registers by threads.
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config SSE_FP_MATH
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bool "Compiler-generated SSEx instructions"
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depends on SSE
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help
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This option allows the compiler to generate SSEx instructions for
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performing floating point math. This can greatly improve performance
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when exactly the same operations are to be performed on multiple
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data objects; however, it can also significantly reduce performance
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when preemptive task switches occur because of the larger register
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set that must be saved and restored.
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Disabling this option means that the compiler utilizes only the
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x87 instruction set for floating point operations.
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config EAGER_FP_SHARING
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bool
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depends on FLOAT
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depends on USERSPACE
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default y if !X86_NO_LAZY_FP
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help
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This hidden option unconditionally saves/restores the FPU/SIMD
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register state on every context switch.
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Mitigates CVE-2018-3665, but incurs a performance hit.
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For vulnerable systems that process sensitive information in the
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FPU register set, should be used any time CONFIG_FLOAT is
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enabled, regardless if the FPU is used by one thread or multiple.
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config LAZY_FP_SHARING
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bool
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depends on FLOAT
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depends on !EAGER_FP_SHARING
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depends on FP_SHARING
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default y if X86_NO_LAZY_FP || !USERSPACE
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help
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This hidden option allows multiple threads to use the floating point
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registers, using logic to lazily save/restore the floating point
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register state on context switch.
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On Intel Core procesors, may be vulnerable to exploits which allows
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malware to read the contents of all floating point registers, see
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CVE-2018-3665.
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endmenu
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config CACHE_LINE_SIZE_DETECT
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bool "Detect cache line size at runtime"
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default y
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help
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This option enables querying the CPUID register for finding the cache line
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size at the expense of taking more memory and code and a slightly increased
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boot time.
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If the CPU's cache line size is known in advance, disable this option and
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manually enter the value for CACHE_LINE_SIZE.
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config CACHE_LINE_SIZE
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int "Cache line size" if !CACHE_LINE_SIZE_DETECT
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default 64 if CPU_ATOM
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default 0
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help
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Size in bytes of a CPU cache line.
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Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
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config CLFLUSH_INSTRUCTION_SUPPORTED
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bool "CLFLUSH instruction supported"
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depends on !CLFLUSH_DETECT && CACHE_FLUSHING
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help
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An implementation of sys_cache_flush() that uses CLFLUSH is made
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available, instead of the one using WBINVD.
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This option should only be enabled if it is known in advance that the
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CPU supports the CLFLUSH instruction. It disables runtime detection of
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CLFLUSH support thereby reducing both memory footprint and boot time.
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config CLFLUSH_DETECT
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bool "Detect support of CLFLUSH instruction at runtime"
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depends on CACHE_FLUSHING
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help
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This option should be enabled if it is not known in advance whether the
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CPU supports the CLFLUSH instruction or not.
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The CPU is queried at boot time to determine which of the multiple
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implementations of sys_cache_flush() linked into the image is the
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correct one to use.
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If the CPU's support (or lack thereof) of CLFLUSH is known in advance, then
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disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate.
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config ARCH_CACHE_FLUSH_DETECT
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bool
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default y
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depends on CLFLUSH_DETECT
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config CACHE_FLUSHING
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bool "Enable cache flushing mechanism"
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help
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This links in the sys_cache_flush() function. A mechanism for flushing the
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cache must be selected as well. By default, that mechanism is discovered at
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runtime.
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config X86_KERNEL_OOPS
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bool "Enable handling of kernel oops as an exception"
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default y
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help
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Enable handling of k_oops() API as a CPU exception, which will provide
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extra debugging information such as program counter and register
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values when the oops is triggered. Requires an entry in the IDT.
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config X86_KERNEL_OOPS_VECTOR
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int "IDT vector to use for kernel oops"
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default 62 if MVIC
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default 33 if !MVIC
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range 32 255
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depends on X86_KERNEL_OOPS
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help
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Specify the IDT vector to use for the kernel oops exception handler.
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The default should be fine for most arches, but on systems like MVIC
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where there is a fixed IRQ-to-vector mapping another value may be
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needed to avoid collision.
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config IRQ_OFFLOAD_VECTOR
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int "IDT vector to use for IRQ offload"
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default 63 if MVIC
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default 32 if !MVIC
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range 32 255
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depends on IRQ_OFFLOAD
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help
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Specify the IDT vector to use for the IRQ offload interrupt handler.
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The default should be fine for most arches, but on systems like MVIC
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where there is a fixed IRQ-to-vector mapping another value may be
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needed to avoid collision.
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config X86_DYNAMIC_IRQ_STUBS
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int "Number of dynamic interrupt stubs"
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depends on DYNAMIC_INTERRUPTS
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default 4
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help
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Installing interrupt handlers with irq_connect_dynamic() requires
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some stub code to be generated at build time, one stub per dynamic
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interrupt.
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config X86_FIXED_IRQ_MAPPING
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bool
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help
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Specify whether the current interrupt controller in use has a fixed
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mapping between IDT vectors and IRQ lines.
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||
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|
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||
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|
endmenu
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||
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|
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||
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endif # !X86_LONGMODE
|