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zephyr/soc/arm/nxp_imx/mcimx7_m4/dts_fixup.h

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arch: Add imx7d m4 soc support The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual Cortex A7 core and Single Cortex M4 core. Zephyr was ported to run on the M4 core. In a later release, it will also communicate with the A7 core (running Linux) via RPmsg. The low level drivers come from NXP FreeRTOS BSP and are located at ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README The A7 core is responsible to load the M4 binary application into the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get the M4 out of reset. The A7 can perform these steps at bootloader level after the Linux system has booted. The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4: +---------------+-----------------+---------------------------+ | Memory Name | Start Address | Size | +===============+=================+===========================+ | TCML | 0x007F8000 | 32KB | +---------------+-----------------+---------------------------+ | TCMU | 0x20000000 | 32KB | +---------------+-----------------+---------------------------+ | OCRAM_S | 0x20180000 | 32KB | +---------------+-----------------+---------------------------+ | OCRAM | 0x00900000 | 128KB | +---------------+-----------------+---------------------------+ | DDR | 0x10000000 | 256MB | +---------------+-----------------+---------------------------+ Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-03-16 13:59:33 +00:00
/*
* Copyright (c) 2018, Diego Sueiro <diego.sueiro@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
drivers/ipm: Add IPM support for i.MX7 This patch ads the support for the IPM drivers on i.MX7 SoC family. Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-11-19 17:42:40 +00:00
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
dts_fixups: Use DT_ prefix in all defined labels not related to Kconfig These changes were obtained by running a script created by Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following specification: 1. Read the contents of all dts_fixup.h files in Zephyr 2. Check the left-hand side of the #define macros (i.e. the X in #define X Y) 3. Check if that name is also the name of a Kconfig option 3.a If it is, then do nothing 3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it has neither of these two prefixes 4. Replace the use of the changed #define in the code itself (.c, .h, .ld) Additionally, some tweaks had to be added to this script to catch some of the macros used in the code in a parameterized form, e.g.: - CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS - CONFIG_UART_##idx##_TX_PIN - I2C_SBCON_##_num##_BASE_ADDR and to prevent adding DT_ prefix to the following symbols: - FLASH_START - FLASH_SIZE - SRAM_START - SRAM_SIZE - _ROM_ADDR - _ROM_SIZE - _RAM_ADDR - _RAM_SIZE which are surprisingly also defined in some dts_fixup.h files. Finally, some manual corrections had to be done as well: - name##_IRQ -> DT_##name##_IRQ in uart_stm32.c Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-11-13 15:15:23 +01:00
drivers/ipm: Add IPM support for i.MX7 This patch ads the support for the IPM drivers on i.MX7 SoC family. Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-11-19 17:42:40 +00:00
#define DT_IPM_IMX_MU_B_BASE_ADDRESS DT_NXP_IMX_MU_30AB0000_BASE_ADDRESS
#define DT_IPM_IMX_MU_B_IRQ DT_NXP_IMX_MU_30AB0000_IRQ_0
#define DT_IPM_IMX_MU_B_IRQ_PRI DT_NXP_IMX_MU_30AB0000_IRQ_0_PRIORITY
#define DT_IPM_IMX_MU_B_NAME DT_NXP_IMX_MU_30AB0000_LABEL
arch: Add imx7d m4 soc support The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual Cortex A7 core and Single Cortex M4 core. Zephyr was ported to run on the M4 core. In a later release, it will also communicate with the A7 core (running Linux) via RPmsg. The low level drivers come from NXP FreeRTOS BSP and are located at ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README The A7 core is responsible to load the M4 binary application into the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get the M4 out of reset. The A7 can perform these steps at bootloader level after the Linux system has booted. The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4: +---------------+-----------------+---------------------------+ | Memory Name | Start Address | Size | +===============+=================+===========================+ | TCML | 0x007F8000 | 32KB | +---------------+-----------------+---------------------------+ | TCMU | 0x20000000 | 32KB | +---------------+-----------------+---------------------------+ | OCRAM_S | 0x20180000 | 32KB | +---------------+-----------------+---------------------------+ | OCRAM | 0x00900000 | 128KB | +---------------+-----------------+---------------------------+ | DDR | 0x10000000 | 256MB | +---------------+-----------------+---------------------------+ Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
2018-03-16 13:59:33 +00:00
/* End of SoC Level DTS fixup file */
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