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zephyr/soc/xtensa/intel_s1000/CMakeLists.txt

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license: cleanup: add SPDX Apache-2.0 license identifier Update the files which contain no license information with the 'Apache-2.0' SPDX license identifier. Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of Zephyr, which is Apache version 2. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-06 09:08:09 -04:00
# SPDX-License-Identifier: Apache-2.0
xtensa: intel_s1000: implement interrupt mechanism intel_s1000 has multiple levels of interrupts consisting of core, CAVS Logic and designware interrupt controller. This patchset modifies the regular gen_isr mechanism to support these multiple levels. Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-12 18:32:23 +05:30
zephyr_library()
cmake: replace PROJECT_SOURCE_DIR with ZEPHYR_BASE Both variables were used (with the same value) interchangeably throughout CMake files and per the discussion in GH issue, ZEPHYR_BASE is preferred. Also add a comment with explanation of one vs. the other. Tested by building hello_world for several boards ensuring no errors. Fixes #7173. Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
2018-06-14 20:21:18 +02:00
zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
xtensa: intel_s1000: implement interrupt mechanism intel_s1000 has multiple levels of interrupts consisting of core, CAVS Logic and designware interrupt controller. This patchset modifies the regular gen_isr mechanism to support these multiple levels. Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-12 18:32:23 +05:30
zephyr_library_sources(soc.c)
soc: intel_s1000_crb: fix XCC build error with newlib The Newlib in the XCC toolchain for intel_s1000_crb has a few missing functions which are reentrant versions of the one defined in lib/libc/newlib/libc-hooks.c. So make these call the correct functions. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-11-26 14:19:36 -08:00
if("${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "xcc")
soc: intel_s1000: move XCC fixes into its own directory Turns out it's going to have more fixes than just Newlib. So put them into one directory. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-12-16 09:35:03 -08:00
add_subdirectory(xcc)
soc: intel_s1000_crb: fix XCC build error with newlib The Newlib in the XCC toolchain for intel_s1000_crb has a few missing functions which are reentrant versions of the one defined in lib/libc/newlib/libc-hooks.c. So make these call the correct functions. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-11-26 14:19:36 -08:00
endif()
soc: intel_s1000: add SMP support This adds SMP support for Intel S1000 SoC. Some of the start-up code is borrowed from ESP32. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-02-21 15:05:30 -08:00
if(CONFIG_SMP)
zephyr_library_sources(soc_mp.c)
endif()
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