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zephyr/tests/application_development/code_relocation/testcase.yaml

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tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
common:
tags: linker
tests:
tests: remove tests. prefix from identifier We know this is a test already. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-08-01 12:01:34 +00:00
application_development.code_relocation:
tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
filter: not CONFIG_CPU_HAS_NXP_MPU and CONFIG_MINIMAL_LIBC and dt_chosen_enabled("zephyr,itcm")
arch/riscv: support CONFIG_CODE_DATA_RELOCATION This implements support for relocating code to chosen memory regions via the `zephyr_code_relocate` CMake function for RISC-V SoCs. ARM-specific assumptions that were made by gen_relocate_app.py need to be corrected, in particular not assuming any particular name for the default RAM section (which is 'SRAM' for most ARM pltaforms) and not assuming 32-bit pointers (so the test works on RV64). Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-08-19 15:29:10 +10:00
arch_allow: arm
tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
extra_configs:
- CONFIG_RELOCATE_TO_ITCM=y
tests: code_relocation: restrict Arm test to NXP platforms Currently tests.application_development.code_relocation and tests.application_development.code_relocation_kinetis scenarios are restricted to specific NXP platforms only, so make filters more strict. Also for frdm_k64f, which lacks of ITCM, relocation to ITCM must be disabled. Fixes #60167 Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-11 11:43:02 -03:00
platform_allow:
- mimxrt1060_evk
tests: remove tests. prefix from identifier We know this is a test already. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-08-01 12:01:34 +00:00
application_development.code_relocation_kinetis:
tests: code_relocation: restrict Arm test to NXP platforms Currently tests.application_development.code_relocation and tests.application_development.code_relocation_kinetis scenarios are restricted to specific NXP platforms only, so make filters more strict. Also for frdm_k64f, which lacks of ITCM, relocation to ITCM must be disabled. Fixes #60167 Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-11 11:43:02 -03:00
filter: CONFIG_CPU_HAS_NXP_MPU and CONFIG_MINIMAL_LIBC
arch/riscv: support CONFIG_CODE_DATA_RELOCATION This implements support for relocating code to chosen memory regions via the `zephyr_code_relocate` CMake function for RISC-V SoCs. ARM-specific assumptions that were made by gen_relocate_app.py need to be corrected, in particular not assuming any particular name for the default RAM section (which is 'SRAM' for most ARM pltaforms) and not assuming 32-bit pointers (so the test works on RV64). Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-08-19 15:29:10 +10:00
arch_allow: arm
tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
extra_configs:
- CONFIG_MPU_ALLOW_FLASH_WRITE=y
tests: code_relocation: restrict Arm test to NXP platforms Currently tests.application_development.code_relocation and tests.application_development.code_relocation_kinetis scenarios are restricted to specific NXP platforms only, so make filters more strict. Also for frdm_k64f, which lacks of ITCM, relocation to ITCM must be disabled. Fixes #60167 Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-11 11:43:02 -03:00
platform_allow:
- frdm_k64f
tests: remove tests. prefix from identifier We know this is a test already. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-08-01 12:01:34 +00:00
application_development.code_relocation.nxp_s32:
tests: code_relocation: support mr_canhubk3 boards Add test scenario for NXP S32 platforms, for now only ported to mr_canhubk3. In some platforms the MPU region used for NULL pointer detection conflicts with the ITCM region, causing access fault. Make disabling the null pointer exception detection the default behavior for this scenario. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-11 11:46:04 -03:00
filter: not CONFIG_CPU_HAS_NXP_MPU and CONFIG_MINIMAL_LIBC and dt_chosen_enabled("zephyr,itcm")
arch_allow: arm
extra_configs:
- CONFIG_RELOCATE_TO_ITCM=y
- CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
platform_allow:
- mr_canhubk3
tests: remove tests. prefix from identifier We know this is a test already. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-08-01 12:01:34 +00:00
application_development.code_relocation.no_itcm:
tests: application_development: add code_relocation test add code relocation test case 1. customer relocation code and data test 2. memcpy relocation Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-07-14 14:48:27 +08:00
filter: not CONFIG_CPU_HAS_NXP_MPU and not dt_chosen_enabled("zephyr,itcm")
arch/riscv: support CONFIG_CODE_DATA_RELOCATION This implements support for relocating code to chosen memory regions via the `zephyr_code_relocate` CMake function for RISC-V SoCs. ARM-specific assumptions that were made by gen_relocate_app.py need to be corrected, in particular not assuming any particular name for the default RAM section (which is 'SRAM' for most ARM pltaforms) and not assuming 32-bit pointers (so the test works on RV64). Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-08-19 15:29:10 +10:00
arch_allow: arm
samples, tests: convert string-based twister lists to YAML lists Twister now supports using YAML lists for all fields that were written as space-separated lists. Used twister_to_list.py script. Some artifacts on string length are due to how ruamel dumps content. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-05-08 13:37:42 +02:00
extra_sections:
- _SRAM2_RODATA_SECTION_NAME
- _SRAM_TEXT_SECTION_NAME
- _SRAM_RODATA_SECTION_NAME
- _SRAM_DATA_SECTION_NAME
- _CUSTOM_SECTION_NAME2
platform_allow:
- qemu_cortex_m3
- mps2_an385
- sam_e70_xplained
tests/samples: use integration_plaforms in more tests/samples integration_platforms help us control what get built/executed in CI and for each PR submitted. They do not filter out platforms, instead they just minimize the amount of builds/testing for a particular tests/sample. Tests still run on all supported platforms when not in integration mode. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-11-29 00:23:08 +00:00
integration_platforms:
- qemu_cortex_m3
tests: remove tests. prefix from identifier We know this is a test already. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-08-01 12:01:34 +00:00
application_development.code_relocation.riscv:
arch/riscv: support CONFIG_CODE_DATA_RELOCATION This implements support for relocating code to chosen memory regions via the `zephyr_code_relocate` CMake function for RISC-V SoCs. ARM-specific assumptions that were made by gen_relocate_app.py need to be corrected, in particular not assuming any particular name for the default RAM section (which is 'SRAM' for most ARM pltaforms) and not assuming 32-bit pointers (so the test works on RV64). Signed-off-by: Peter Marheine <pmarheine@chromium.org>
2022-08-19 15:29:10 +10:00
extra_args: CONF_FILE="prj_riscv.conf"
samples, tests: convert string-based twister lists to YAML lists Twister now supports using YAML lists for all fields that were written as space-separated lists. Used twister_to_list.py script. Some artifacts on string length are due to how ruamel dumps content. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-05-08 13:37:42 +02:00
platform_allow:
- qemu_riscv32
- qemu_riscv64
tests: remove tests. prefix from identifier We know this is a test already. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-08-01 12:01:34 +00:00
application_development.code_relocation.xtensa:
arch/xtensa: Enable code relocation Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds support for the "sample_controller" SoC (used by qemu_xtensa) as demonstration. As Xtensa lacks a common linker script at the arch level, enabling it for each platform will be a piecemeal effort. This patch adds it to the `soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is set to be called "RAM", and hooks are inserted so that gen_relocate_app.py can add the relevant linker bits. Also, `tests/application_developent/code_relocation` was tweaked to support the qemu_xtensa platform. Basically, add the relevant linker script and ensure that relevant memory regions have their program header (PHDR) associated. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-10-19 12:25:12 -07:00
extra_args: CONF_FILE="prj_xtensa.conf"
platform_allow: qemu_xtensa
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