2020-06-16 16:55:36 -05:00
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/*
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* Copyright (c) 2020, NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <fsl_iopctl.h>
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#include <soc.h>
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2020-04-30 20:33:38 +02:00
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static int mimxrt685_evk_pinmux_init(const struct device *dev)
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2020-06-16 16:55:36 -05:00
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{
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ARG_UNUSED(dev);
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay) && CONFIG_SERIAL
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/* USART0 RX, TX */
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2021-02-22 11:56:50 -06:00
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uint32_t port0_pin1_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
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2020-06-16 16:55:36 -05:00
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IOPCTL_PIO_FUNC1 |
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/* Disable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_DI |
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/* Enable pull-down function */
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IOPCTL_PIO_PULLDOWN_EN |
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/* Disable input buffer function */
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IOPCTL_PIO_INBUF_DI |
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/* Normal mode */
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IOPCTL_PIO_SLEW_RATE_NORMAL |
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/* Normal drive */
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IOPCTL_PIO_FULLDRIVE_DI |
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/* Analog mux is disabled */
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IOPCTL_PIO_ANAMUX_DI |
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/* Pseudo Output Drain is disabled */
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IOPCTL_PIO_PSEDRAIN_DI |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT0 PIN1 (coords: G2) is configured as FC0_TXD_SCL_MISO_WS */
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IOPCTL_PinMuxSet(IOPCTL, 0U, 1U, port0_pin1_config);
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2021-02-22 11:56:50 -06:00
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uint32_t port0_pin2_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
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2020-06-16 16:55:36 -05:00
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IOPCTL_PIO_FUNC1 |
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/* Disable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_DI |
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/* Enable pull-down function */
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IOPCTL_PIO_PULLDOWN_EN |
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/* Enables input buffer function */
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IOPCTL_PIO_INBUF_EN |
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/* Normal mode */
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IOPCTL_PIO_SLEW_RATE_NORMAL |
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/* Normal drive */
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IOPCTL_PIO_FULLDRIVE_DI |
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/* Analog mux is disabled */
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IOPCTL_PIO_ANAMUX_DI |
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/* Pseudo Output Drain is disabled */
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IOPCTL_PIO_PSEDRAIN_DI |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT0 PIN2 (coords: G4) is configured as FC0_RXD_SDA_MOSI_DATA */
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IOPCTL_PinMuxSet(IOPCTL, 0U, 2U, port0_pin2_config);
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#endif
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#if DT_PHA_HAS_CELL(DT_ALIAS(sw0), gpios, pin)
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2021-02-22 11:56:50 -06:00
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uint32_t port1_pin1_config = (/* Pin is configured as PIO1_1 */
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2020-06-16 16:55:36 -05:00
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IOPCTL_PIO_FUNC0 |
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/* Disable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_DI |
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/* Enable pull-down function */
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IOPCTL_PIO_PULLDOWN_EN |
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/* Enables input buffer function */
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IOPCTL_PIO_INBUF_EN |
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/* Normal mode */
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IOPCTL_PIO_SLEW_RATE_NORMAL |
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/* Normal drive */
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IOPCTL_PIO_FULLDRIVE_DI |
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/* Analog mux is disabled */
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IOPCTL_PIO_ANAMUX_DI |
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/* Pseudo Output Drain is disabled */
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IOPCTL_PIO_PSEDRAIN_DI |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT1 PIN1 (coords: G15) is configured as PIO1_1 */
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IOPCTL_PinMuxSet(IOPCTL, 1U, 1U, port1_pin1_config);
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#endif
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#if DT_PHA_HAS_CELL(DT_ALIAS(sw1), gpios, pin)
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uint32_t port0_pin10_config = (/* Pin is configured as PIO0_10 */
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2020-06-16 16:55:36 -05:00
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IOPCTL_PIO_FUNC0 |
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/* Disable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_DI |
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/* Enable pull-down function */
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IOPCTL_PIO_PULLDOWN_EN |
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/* Enables input buffer function */
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IOPCTL_PIO_INBUF_EN |
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/* Normal mode */
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IOPCTL_PIO_SLEW_RATE_NORMAL |
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/* Normal drive */
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IOPCTL_PIO_FULLDRIVE_DI |
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/* Analog mux is disabled */
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IOPCTL_PIO_ANAMUX_DI |
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/* Pseudo Output Drain is disabled */
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IOPCTL_PIO_PSEDRAIN_DI |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT0 PIN10 (coords: J3) is configured as PIO0_10 */
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IOPCTL_PinMuxSet(IOPCTL, 0U, 10U, port0_pin10_config);
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#endif
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#ifdef DT_GPIO_LEDS_LED_1_GPIOS_CONTROLLER
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uint32_t port0_pin14_config = (/* Pin is configured as PIO0_14 */
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2020-06-16 16:55:36 -05:00
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IOPCTL_PIO_FUNC0 |
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/* Disable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_DI |
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/* Enable pull-down function */
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IOPCTL_PIO_PULLDOWN_EN |
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/* Disable input buffer function */
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IOPCTL_PIO_INBUF_DI |
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/* Normal mode */
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IOPCTL_PIO_SLEW_RATE_NORMAL |
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/* Normal drive */
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IOPCTL_PIO_FULLDRIVE_DI |
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/* Analog mux is disabled */
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IOPCTL_PIO_ANAMUX_DI |
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/* Pseudo Output Drain is disabled */
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IOPCTL_PIO_PSEDRAIN_DI |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT0 PIN14 (coords: A3) is configured as PIO0_14 */
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IOPCTL_PinMuxSet(IOPCTL, 0U, 14U, port0_pin14_config);
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#endif
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2020-07-17 08:21:27 -05:00
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_i2c, okay) && CONFIG_I2C
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2021-02-22 11:56:50 -06:00
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uint32_t port0_pin17_config = (/* Pin is configured as FC2_CTS_SDA_SSEL0 */
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2020-07-17 08:21:27 -05:00
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IOPCTL_PIO_FUNC1 |
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/* Enable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_EN |
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/* Enable pull-up function */
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IOPCTL_PIO_PULLUP_EN |
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/* Enables input buffer function */
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IOPCTL_PIO_INBUF_EN |
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/* Normal mode */
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IOPCTL_PIO_SLEW_RATE_NORMAL |
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/* Full drive enable */
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IOPCTL_PIO_FULLDRIVE_EN |
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/* Analog mux is disabled */
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IOPCTL_PIO_ANAMUX_DI |
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/* Pseudo Output Drain is enabled */
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IOPCTL_PIO_PSEDRAIN_EN |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT0 PIN17 (coords: D7) is configured as FC2_CTS_SDA_SSEL0 */
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IOPCTL_PinMuxSet(IOPCTL, 0U, 17U, port0_pin17_config);
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2021-02-22 11:56:50 -06:00
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uint32_t port0_pin18_config = (/* Pin is configured as FC2_RTS_SCL_SSEL1 */
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2020-07-17 08:21:27 -05:00
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IOPCTL_PIO_FUNC1 |
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/* Enable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_EN |
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/* Enable pull-up function */
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IOPCTL_PIO_PULLUP_EN |
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/* Enables input buffer function */
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IOPCTL_PIO_INBUF_EN |
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/* Normal mode */
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IOPCTL_PIO_SLEW_RATE_NORMAL |
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/* Full drive enable */
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IOPCTL_PIO_FULLDRIVE_EN |
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/* Analog mux is disabled */
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IOPCTL_PIO_ANAMUX_DI |
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/* Pseudo Output Drain is enabled */
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IOPCTL_PIO_PSEDRAIN_EN |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT0 PIN18 (coords: B7) is configured as FC2_RTS_SCL_SSEL1 */
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IOPCTL_PinMuxSet(IOPCTL, 0U, 18U, port0_pin18_config);
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#endif
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#ifdef CONFIG_FXOS8700_TRIGGER
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uint32_t port1_pin5_config = (/* Pin is configured as PIO1_5 */
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2020-07-17 08:21:27 -05:00
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IOPCTL_PIO_FUNC0 |
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/* Disable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_DI |
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/* Enable pull-down function */
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IOPCTL_PIO_PULLDOWN_EN |
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/* Enables input buffer function */
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IOPCTL_PIO_INBUF_EN |
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/* Normal mode */
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IOPCTL_PIO_SLEW_RATE_NORMAL |
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/* Normal drive */
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IOPCTL_PIO_FULLDRIVE_DI |
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/* Analog mux is disabled */
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IOPCTL_PIO_ANAMUX_DI |
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/* Pseudo Output Drain is disabled */
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IOPCTL_PIO_PSEDRAIN_DI |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT1 PIN5 (coords: J16) is configured as PIO1_5 */
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IOPCTL_PinMuxSet(IOPCTL, 1U, 5U, port1_pin5_config);
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#endif
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2020-07-29 07:11:33 -05:00
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm5), okay) && CONFIG_SPI
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uint32_t port1_pin3_config = (/* Pin is configured as FC5_SCK */
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2020-07-29 07:11:33 -05:00
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IOPCTL_PIO_FUNC1 |
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/* Disable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_DI |
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/* Enable pull-down function */
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IOPCTL_PIO_PULLDOWN_EN |
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/* Enables input buffer function */
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IOPCTL_PIO_INBUF_EN |
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/* Normal mode */
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IOPCTL_PIO_SLEW_RATE_NORMAL |
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/* Normal drive */
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IOPCTL_PIO_FULLDRIVE_DI |
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/* Analog mux is disabled */
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IOPCTL_PIO_ANAMUX_DI |
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/* Pseudo Output Drain is disabled */
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IOPCTL_PIO_PSEDRAIN_DI |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT1 PIN3 (coords: G16) is configured as FC5_SCK */
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IOPCTL_PinMuxSet(IOPCTL, 1U, 3U, port1_pin3_config);
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2021-02-22 11:56:50 -06:00
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uint32_t port1_pin4_config = (/* Pin is configured as FC5_MISO */
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IOPCTL_PIO_FUNC1 |
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/* Disable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_DI |
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/* Enable pull-down function */
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IOPCTL_PIO_PULLDOWN_EN |
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/* Enables input buffer function */
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IOPCTL_PIO_INBUF_EN |
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/* Normal mode */
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IOPCTL_PIO_SLEW_RATE_NORMAL |
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/* Normal drive */
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IOPCTL_PIO_FULLDRIVE_DI |
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/* Analog mux is disabled */
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IOPCTL_PIO_ANAMUX_DI |
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/* Pseudo Output Drain is disabled */
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IOPCTL_PIO_PSEDRAIN_DI |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT1 PIN4 (coords: G17) is configured as FC5_TXD_SCL_MISO_WS */
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IOPCTL_PinMuxSet(IOPCTL, 1U, 4U, port1_pin4_config);
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2021-02-22 11:56:50 -06:00
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uint32_t port1_pin5_config = (/* Pin is configured as FC5_MOSI */
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2020-07-29 07:11:33 -05:00
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IOPCTL_PIO_FUNC1 |
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/* Disable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_DI |
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/* Enable pull-down function */
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IOPCTL_PIO_PULLDOWN_EN |
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/* Enables input buffer function */
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IOPCTL_PIO_INBUF_EN |
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/* Normal mode */
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IOPCTL_PIO_SLEW_RATE_NORMAL |
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/* Normal drive */
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IOPCTL_PIO_FULLDRIVE_DI |
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/* Analog mux is disabled */
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IOPCTL_PIO_ANAMUX_DI |
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/* Pseudo Output Drain is disabled */
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IOPCTL_PIO_PSEDRAIN_DI |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT1 PIN5 (coords: J16) is configured as FC5_RXD_SDA_MOSI_DATA */
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IOPCTL_PinMuxSet(IOPCTL, 1U, 5U, port1_pin5_config);
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2021-02-22 11:56:50 -06:00
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uint32_t port1_pin6_config = (/* Pin is configured as FC5_SSEL0 */
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2020-07-29 07:11:33 -05:00
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IOPCTL_PIO_FUNC1 |
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/* Disable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_DI |
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/* Enable pull-down function */
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IOPCTL_PIO_PULLDOWN_EN |
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/* Enables input buffer function */
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IOPCTL_PIO_INBUF_EN |
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/* Normal mode */
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IOPCTL_PIO_SLEW_RATE_NORMAL |
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/* Normal drive */
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IOPCTL_PIO_FULLDRIVE_DI |
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/* Analog mux is disabled */
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IOPCTL_PIO_ANAMUX_DI |
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/* Pseudo Output Drain is disabled */
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IOPCTL_PIO_PSEDRAIN_DI |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT1 PIN6 (coords: J17) is configured as FC5_CTS_SDA_SSEL0 */
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IOPCTL_PinMuxSet(IOPCTL, 1U, 6U, port1_pin6_config);
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#endif
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2021-02-22 14:03:45 -06:00
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#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay)) && \
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(DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay)) && \
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CONFIG_I2S
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/* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm3 */
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SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(3) |
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SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(3);
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#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
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/* Select Data in from Transmit I2S - Flexcomm 3 */
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SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(3);
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/* Enable Transmit I2S - Flexcomm 3 for Shared Data Out */
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SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN(1);
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#endif
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/* Set Receive I2S - Flexcomm 1 SCK, WS from shared signal set 0 */
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SYSCTL1->FCCTRLSEL[1] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
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SYSCTL1_FCCTRLSEL_WSINSEL(1);
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/* Set Transmit I2S - Flexcomm 3 SCK, WS from shared signal set 0 */
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SYSCTL1->FCCTRLSEL[3] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
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SYSCTL1_FCCTRLSEL_WSINSEL(1);
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#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
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/* Select Receive I2S - Flexcomm 1 Data in from shared signal set 0 */
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SYSCTL1->FCCTRLSEL[1] |= SYSCTL1_FCCTRLSEL_DATAINSEL(1);
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/* Select Transmit I2S - Flexcomm 3 Data out to shared signal set 0 */
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SYSCTL1->FCCTRLSEL[3] |= SYSCTL1_FCCTRLSEL_DATAOUTSEL(1);
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#endif
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/* Pin is configured as FC3_RXD_SDA_MOSI_DATA */
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uint32_t port0_pin23_config = (
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IOPCTL_PIO_FUNC1 |
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/* Disable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_DI |
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/* Enable pull-down function */
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IOPCTL_PIO_PULLDOWN_EN |
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/* Enables input buffer function */
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IOPCTL_PIO_INBUF_EN |
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/* Normal mode */
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IOPCTL_PIO_SLEW_RATE_NORMAL |
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/* Full drive enable */
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IOPCTL_PIO_FULLDRIVE_EN |
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/* Analog mux is disabled */
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IOPCTL_PIO_ANAMUX_DI |
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/* Pseudo Output Drain is disabled */
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IOPCTL_PIO_PSEDRAIN_DI |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT0 PIN23 (coords: C9) is configured as FC3_RXD_SDA_MOSI_DATA */
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IOPCTL_PinMuxSet(IOPCTL, 0U, 23U, port0_pin23_config);
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/* Pin is configured as FC3_TXD_SCL_MISO_WS */
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uint32_t port0_pin22_config = (
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IOPCTL_PIO_FUNC1 |
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/* Disable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_DI |
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/* Enable pull-down function */
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IOPCTL_PIO_PULLDOWN_EN |
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/* Enables input buffer function */
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IOPCTL_PIO_INBUF_EN |
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/* Normal mode */
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IOPCTL_PIO_SLEW_RATE_NORMAL |
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/* Full drive enable */
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IOPCTL_PIO_FULLDRIVE_EN |
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/* Analog mux is disabled */
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IOPCTL_PIO_ANAMUX_DI |
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/* Pseudo Output Drain is disabled */
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IOPCTL_PIO_PSEDRAIN_DI |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT0 PIN22 (coords: D8) is configured as FC3_TXD_SCL_MISO_WS */
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IOPCTL_PinMuxSet(IOPCTL, 0U, 22U, port0_pin22_config);
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/* Pin is configured as FC3_SCK */
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uint32_t port0_pin21_config = (
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IOPCTL_PIO_FUNC1 |
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/* Disable pull-up / pull-down function */
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IOPCTL_PIO_PUPD_DI |
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/* Enable pull-down function */
|
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IOPCTL_PIO_PULLDOWN_EN |
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/* Enables input buffer function */
|
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IOPCTL_PIO_INBUF_EN |
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|
|
|
/* Normal mode */
|
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IOPCTL_PIO_SLEW_RATE_NORMAL |
|
|
|
|
/* Full drive enable */
|
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IOPCTL_PIO_FULLDRIVE_EN |
|
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/* Analog mux is disabled */
|
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IOPCTL_PIO_ANAMUX_DI |
|
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|
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/* Pseudo Output Drain is disabled */
|
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IOPCTL_PIO_PSEDRAIN_DI |
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/* Input function is not inverted */
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IOPCTL_PIO_INV_DI);
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/* PORT0 PIN21 (coords: C7) is configured as FC3_SCK */
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|
|
IOPCTL_PinMuxSet(IOPCTL, 0U, 21U, port0_pin21_config);
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/* Pin is configured as FC1_RXD_SDA_MOSI_DATA */
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|
|
uint32_t port0_pin9_config = (
|
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|
|
IOPCTL_PIO_FUNC1 |
|
|
|
|
/* Disable pull-up / pull-down function */
|
|
|
|
IOPCTL_PIO_PUPD_DI |
|
|
|
|
/* Enable pull-down function */
|
|
|
|
IOPCTL_PIO_PULLDOWN_EN |
|
|
|
|
/* Enables input buffer function */
|
|
|
|
IOPCTL_PIO_INBUF_EN |
|
|
|
|
/* Normal mode */
|
|
|
|
IOPCTL_PIO_SLEW_RATE_NORMAL |
|
|
|
|
/* Full drive enable */
|
|
|
|
IOPCTL_PIO_FULLDRIVE_EN |
|
|
|
|
/* Analog mux is disabled */
|
|
|
|
IOPCTL_PIO_ANAMUX_DI |
|
|
|
|
/* Pseudo Output Drain is disabled */
|
|
|
|
IOPCTL_PIO_PSEDRAIN_DI |
|
|
|
|
/* Input function is not inverted */
|
|
|
|
IOPCTL_PIO_INV_DI);
|
|
|
|
/* PORT0 PIN9 (coords: L3) is configured as FC1_RXD_SDA_MOSI_DATA */
|
|
|
|
IOPCTL_PinMuxSet(IOPCTL, 0U, 9U, port0_pin9_config);
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|
|
#endif
|
|
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|
|
2020-06-16 16:55:36 -05:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-04-17 10:37:37 -05:00
|
|
|
/* priority set to CONFIG_PINMUX_INIT_PRIORITY value */
|
|
|
|
SYS_INIT(mimxrt685_evk_pinmux_init, PRE_KERNEL_1, 45);
|