589 lines
16 KiB
Text
589 lines
16 KiB
Text
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/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* Linker script for the Xtensa platform.
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*/
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#include <xtensa/config/core-isa.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/linker/linker-tool.h>
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#define RAMABLE_REGION RAM :sram0_phdr
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#define ROMABLE_REGION RAM :sram0_phdr
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#ifdef CONFIG_MPU
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#define MPU_SEGMENT_SIZE_ALIGN . = ALIGN(XCHAL_MPU_ALIGN);
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#define HDR_MPU_SEGMENT_SIZE_ALIGN ALIGN(XCHAL_MPU_ALIGN)
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#define HDR_4K_OR_MPU_SEGMENT_SIZE_ALIGN ALIGN(XCHAL_MPU_ALIGN)
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#define LAST_RAM_ALIGN MPU_SEGMENT_SIZE_ALIGN
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#else
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#define MPU_SEGMENT_SIZE_ALIGN . = ALIGN(4);
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#define HDR_MPU_SEGMENT_SIZE_ALIGN ALIGN(4)
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#define HDR_4K_OR_MPU_SEGMENT_SIZE_ALIGN ALIGN(4096)
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#endif
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#define PHYS_SRAM0_ADDR (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define PHYS_SRAM0_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#define PHYS_ROM0_ADDR (DT_REG_ADDR(DT_NODELABEL(srom0)))
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#define PHYS_ROM0_SIZE (DT_REG_SIZE(DT_NODELABEL(srom0)))
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/* Usable RAM is after the exception vectors and page-aligned. */
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#define PHYS_RAM_ADDR (PHYS_SRAM0_ADDR + CONFIG_SRAM_OFFSET)
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#define PHYS_RAM_SIZE (PHYS_SRAM0_SIZE - CONFIG_SRAM_OFFSET)
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MEMORY
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{
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dram1_0_seg : org = 0x3FFC0000, len = 0x20000
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dram0_0_seg : org = 0x3FFE0000, len = 0x20000
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iram0_0_seg : org = 0x40000000, len = 0x178
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iram0_1_seg : org = 0x40000178, len = 0x8
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iram0_2_seg : org = 0x40000180, len = 0x38
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iram0_3_seg : org = 0x400001B8, len = 0x8
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iram0_4_seg : org = 0x400001C0, len = 0x38
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iram0_5_seg : org = 0x400001F8, len = 0x8
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iram0_6_seg : org = 0x40000200, len = 0x38
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iram0_7_seg : org = 0x40000238, len = 0x8
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iram0_8_seg : org = 0x40000240, len = 0x38
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iram0_9_seg : org = 0x40000278, len = 0x8
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iram0_10_seg : org = 0x40000280, len = 0x38
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iram0_11_seg : org = 0x400002B8, len = 0x8
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iram0_12_seg : org = 0x400002C0, len = 0x38
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iram0_13_seg : org = 0x400002F8, len = 0x8
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iram0_14_seg : org = 0x40000300, len = 0x38
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iram0_15_seg : org = 0x40000338, len = 0x8
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iram0_16_seg : org = 0x40000340, len = 0x38
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iram0_17_seg : org = 0x40000378, len = 0x48
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iram0_18_seg : org = 0x400003C0, len = 0x40
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iram0_19_seg : org = 0x40000400, len = 0x1FC00
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#ifdef CONFIG_MPU
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vec_helpers : org = 0x40002400, len = (PHYS_RAM_ADDR - 0x00002400)
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#endif
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srom0_seg : org = PHYS_ROM0_ADDR, len = PHYS_ROM0_SIZE
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RAM : org = PHYS_RAM_ADDR, len = PHYS_RAM_SIZE
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#ifdef CONFIG_GEN_ISR_TABLES
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/* The space before exception vectors is not being used.
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* So we stuff the temporary IDT_LIST there to avoid
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* some linker issues which would balloon the size of
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* the intermediate files (like zephyr_pre0.elf, to
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* couple hundred MBs or even GBs).
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*/
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IDT_LIST : org = 0x3FFBE000, len = 0x2000
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#endif
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}
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PHDRS
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{
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dram1_0_phdr PT_LOAD;
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dram1_0_bss_phdr PT_LOAD;
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dram0_0_phdr PT_LOAD;
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dram0_0_bss_phdr PT_LOAD;
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iram0_0_phdr PT_LOAD;
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iram0_1_phdr PT_LOAD;
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iram0_2_phdr PT_LOAD;
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iram0_3_phdr PT_LOAD;
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iram0_4_phdr PT_LOAD;
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iram0_5_phdr PT_LOAD;
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iram0_6_phdr PT_LOAD;
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iram0_7_phdr PT_LOAD;
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iram0_8_phdr PT_LOAD;
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iram0_9_phdr PT_LOAD;
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iram0_10_phdr PT_LOAD;
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iram0_11_phdr PT_LOAD;
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iram0_12_phdr PT_LOAD;
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iram0_13_phdr PT_LOAD;
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iram0_14_phdr PT_LOAD;
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iram0_15_phdr PT_LOAD;
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iram0_16_phdr PT_LOAD;
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iram0_17_phdr PT_LOAD;
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iram0_18_phdr PT_LOAD;
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#ifdef CONFIG_XTENSA_MPU
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vec_helpers_phdr PT_LOAD;
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#endif
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srom0_phdr PT_LOAD;
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sram0_phdr PT_LOAD;
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sram0_bss_phdr PT_LOAD;
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}
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/* Default entry point: */
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ENTRY(CONFIG_KERNEL_ENTRY)
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_rom_store_table = 0;
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PROVIDE(_memmap_vecbase_reset = 0x40000000);
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PROVIDE(_memmap_reset_vector = 0x50000000);
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/* Various memory-map dependent cache attribute settings: */
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_memmap_cacheattr_wb_base = 0x00001110;
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_memmap_cacheattr_wt_base = 0x00001110;
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_memmap_cacheattr_bp_base = 0x00002220;
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_memmap_cacheattr_unused_mask = 0xFFFF000F;
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_memmap_cacheattr_wb_trapnull = 0x2222111F;
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_memmap_cacheattr_wba_trapnull = 0x2222111F;
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_memmap_cacheattr_wbna_trapnull = 0x2222111F;
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_memmap_cacheattr_wt_trapnull = 0x2222111F;
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_memmap_cacheattr_bp_trapnull = 0x2222222F;
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_memmap_cacheattr_wb_strict = 0xFFFF111F;
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_memmap_cacheattr_wt_strict = 0xFFFF111F;
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_memmap_cacheattr_bp_strict = 0xFFFF222F;
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_memmap_cacheattr_wb_allvalid = 0x22221112;
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_memmap_cacheattr_wt_allvalid = 0x22221112;
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_memmap_cacheattr_bp_allvalid = 0x22222222;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_bp_trapnull);
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SECTIONS
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{
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#include <zephyr/linker/rel-sections.ld>
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <zephyr/linker/intlist.ld>
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#endif
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.dram1.rodata : ALIGN(4)
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{
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_dram1_rodata_start = ABSOLUTE(.);
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*(.dram1.rodata)
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_dram1_rodata_end = ABSOLUTE(.);
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} >dram1_0_seg :dram1_0_phdr
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.dram1.literal : ALIGN(4)
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{
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_dram1_literal_start = ABSOLUTE(.);
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*(.dram1.literal)
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_dram1_literal_end = ABSOLUTE(.);
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} >dram1_0_seg :dram1_0_phdr
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.dram1.data : ALIGN(4)
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{
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_dram1_data_start = ABSOLUTE(.);
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*(.dram1.data)
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_dram1_data_end = ABSOLUTE(.);
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} >dram1_0_seg :dram1_0_phdr
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.dram1.bss (NOLOAD) : ALIGN(8)
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{
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. = ALIGN (8);
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_dram1_bss_start = ABSOLUTE(.);
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*(.dram1.bss)
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. = ALIGN (8);
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_dram1_bss_end = ABSOLUTE(.);
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_memmap_seg_dram1_0_end = ALIGN(0x8);
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} >dram1_0_seg :dram1_0_bss_phdr
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.dram0.rodata : ALIGN(4)
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{
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_dram0_rodata_start = ABSOLUTE(.);
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*(.dram0.rodata)
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_dram0_rodata_end = ABSOLUTE(.);
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} >dram0_0_seg :dram0_0_phdr
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.dram0.literal : ALIGN(4)
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{
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_dram0_literal_start = ABSOLUTE(.);
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*(.dram0.literal)
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_dram0_literal_end = ABSOLUTE(.);
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} >dram0_0_seg :dram0_0_phdr
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.dram0.data : ALIGN(4)
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{
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_dram0_data_start = ABSOLUTE(.);
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*(.dram0.data)
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_dram0_data_end = ABSOLUTE(.);
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} >dram0_0_seg :dram0_0_phdr
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.dram0.bss (NOLOAD) : ALIGN(8)
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{
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. = ALIGN (8);
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_dram0_bss_start = ABSOLUTE(.);
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*(.dram0.bss)
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. = ALIGN (8);
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_dram0_bss_end = ABSOLUTE(.);
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_memmap_seg_dram0_0_end = ALIGN(0x8);
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} >dram0_0_seg :dram0_0_bss_phdr
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.WindowVectors.text : ALIGN(4)
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{
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_WindowVectors_text_start = ABSOLUTE(.);
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KEEP (*(.WindowVectors.text))
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_WindowVectors_text_end = ABSOLUTE(.);
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} >iram0_0_seg :iram0_0_phdr
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.Level2InterruptVector.literal : ALIGN(4)
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{
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_Level2InterruptVector_literal_start = ABSOLUTE(.);
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*(.Level2InterruptVector.literal)
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_Level2InterruptVector_literal_end = ABSOLUTE(.);
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} >iram0_1_seg :iram0_1_phdr
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.Level2InterruptVector.text : ALIGN(4)
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{
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_Level2InterruptVector_text_start = ABSOLUTE(.);
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KEEP (*(.Level2InterruptVector.text))
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_Level2InterruptVector_text_end = ABSOLUTE(.);
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} >iram0_2_seg :iram0_2_phdr
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.Level3InterruptVector.literal : ALIGN(4)
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{
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_Level3InterruptVector_literal_start = ABSOLUTE(.);
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*(.Level3InterruptVector.literal)
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_Level3InterruptVector_literal_end = ABSOLUTE(.);
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} >iram0_3_seg :iram0_3_phdr
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.Level3InterruptVector.text : ALIGN(4)
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{
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_Level3InterruptVector_text_start = ABSOLUTE(.);
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KEEP (*(.Level3InterruptVector.text))
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_Level3InterruptVector_text_end = ABSOLUTE(.);
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} >iram0_4_seg :iram0_4_phdr
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.Level4InterruptVector.literal : ALIGN(4)
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{
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_Level4InterruptVector_literal_start = ABSOLUTE(.);
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*(.Level4InterruptVector.literal)
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_Level4InterruptVector_literal_end = ABSOLUTE(.);
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} >iram0_5_seg :iram0_5_phdr
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.Level4InterruptVector.text : ALIGN(4)
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{
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_Level4InterruptVector_text_start = ABSOLUTE(.);
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KEEP (*(.Level4InterruptVector.text))
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_Level4InterruptVector_text_end = ABSOLUTE(.);
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} >iram0_6_seg :iram0_6_phdr
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.Level5InterruptVector.literal : ALIGN(4)
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{
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_Level5InterruptVector_literal_start = ABSOLUTE(.);
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*(.Level5InterruptVector.literal)
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_Level5InterruptVector_literal_end = ABSOLUTE(.);
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} >iram0_7_seg :iram0_7_phdr
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.Level5InterruptVector.text : ALIGN(4)
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{
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_Level5InterruptVector_text_start = ABSOLUTE(.);
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KEEP (*(.Level5InterruptVector.text))
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_Level5InterruptVector_text_end = ABSOLUTE(.);
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} >iram0_8_seg :iram0_8_phdr
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.DebugExceptionVector.literal : ALIGN(4)
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{
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_DebugExceptionVector_literal_start = ABSOLUTE(.);
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*(.DebugExceptionVector.literal)
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_DebugExceptionVector_literal_end = ABSOLUTE(.);
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} >iram0_9_seg :iram0_9_phdr
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.DebugExceptionVector.text : ALIGN(4)
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{
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_DebugExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.DebugExceptionVector.text))
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_DebugExceptionVector_text_end = ABSOLUTE(.);
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} >iram0_10_seg :iram0_10_phdr
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.NMIExceptionVector.literal : ALIGN(4)
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{
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_NMIExceptionVector_literal_start = ABSOLUTE(.);
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*(.NMIExceptionVector.literal)
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_NMIExceptionVector_literal_end = ABSOLUTE(.);
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} >iram0_11_seg :iram0_11_phdr
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.NMIExceptionVector.text : ALIGN(4)
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{
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_NMIExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.NMIExceptionVector.text))
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_NMIExceptionVector_text_end = ABSOLUTE(.);
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} >iram0_12_seg :iram0_12_phdr
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.KernelExceptionVector.literal : ALIGN(4)
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{
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_KernelExceptionVector_literal_start = ABSOLUTE(.);
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*(.KernelExceptionVector.literal)
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_KernelExceptionVector_literal_end = ABSOLUTE(.);
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} >iram0_13_seg :iram0_13_phdr
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.KernelExceptionVector.text : ALIGN(4)
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{
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_KernelExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.KernelExceptionVector.text))
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_KernelExceptionVector_text_end = ABSOLUTE(.);
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} >iram0_14_seg :iram0_14_phdr
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.UserExceptionVector.literal : ALIGN(4)
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{
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|
|
_UserExceptionVector_literal_start = ABSOLUTE(.);
|
||
|
|
*(.UserExceptionVector.literal)
|
||
|
|
_UserExceptionVector_literal_end = ABSOLUTE(.);
|
||
|
|
} >iram0_15_seg :iram0_15_phdr
|
||
|
|
|
||
|
|
.UserExceptionVector.text : ALIGN(4)
|
||
|
|
{
|
||
|
|
_UserExceptionVector_text_start = ABSOLUTE(.);
|
||
|
|
KEEP (*(.UserExceptionVector.text))
|
||
|
|
_UserExceptionVector_text_end = ABSOLUTE(.);
|
||
|
|
} >iram0_16_seg :iram0_16_phdr
|
||
|
|
|
||
|
|
.DoubleExceptionVector.literal : ALIGN(4)
|
||
|
|
{
|
||
|
|
_DoubleExceptionVector_literal_start = ABSOLUTE(.);
|
||
|
|
*(.DoubleExceptionVector.literal)
|
||
|
|
_DoubleExceptionVector_literal_end = ABSOLUTE(.);
|
||
|
|
} >iram0_17_seg :iram0_17_phdr
|
||
|
|
|
||
|
|
.DoubleExceptionVector.text : ALIGN(4)
|
||
|
|
{
|
||
|
|
_DoubleExceptionVector_text_start = ABSOLUTE(.);
|
||
|
|
KEEP (*(.DoubleExceptionVector.text))
|
||
|
|
_DoubleExceptionVector_text_end = ABSOLUTE(.);
|
||
|
|
} >iram0_18_seg :iram0_18_phdr
|
||
|
|
|
||
|
|
#define LIB_OBJ_FUNC_IN_SECT(library, obj_file, func) \
|
||
|
|
*##library##:##obj_file##(.literal.##func .text.##func) \
|
||
|
|
|
||
|
|
#ifdef CONFIG_XTENSA_MPU
|
||
|
|
.vec_helpers :
|
||
|
|
{
|
||
|
|
/* There is quite some space between .DoubleExceptionVector
|
||
|
|
* and the beginning of .text. We can put exception handling
|
||
|
|
* code here.
|
||
|
|
*/
|
||
|
|
|
||
|
|
*libarch__xtensa__core.a:xtensa_asm2_util.S.obj(.literal .text)
|
||
|
|
*libarch__xtensa__core.a:xtensa_asm2_util.S.obj(.iram.text .iram0.text)
|
||
|
|
|
||
|
|
*libarch__xtensa__core.a:window_vectors.S.obj(.iram.text)
|
||
|
|
|
||
|
|
*libarch__xtensa__core.a:crt1.S.obj(.literal .text)
|
||
|
|
|
||
|
|
LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,xtensa_asm2.c.obj,*)
|
||
|
|
LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,fatal.c.obj,*)
|
||
|
|
LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,cpu_idle.c.obj,*)
|
||
|
|
|
||
|
|
*(.literal.arch_is_in_isr .text.arch_is_in_isr)
|
||
|
|
|
||
|
|
/* To support backtracing */
|
||
|
|
LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,xtensa_backtrace.c.obj,*)
|
||
|
|
|
||
|
|
*libarch__xtensa__core.a:debug_helpers_asm.S.obj(.iram1.literal .iram1)
|
||
|
|
|
||
|
|
/* Userspace related stuff */
|
||
|
|
LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,userspace.S.obj,xtensa_do_syscall)
|
||
|
|
|
||
|
|
/* Below are to speed up execution by avoiding TLB misses
|
||
|
|
* on frequently used functions.
|
||
|
|
*
|
||
|
|
* There is almost 1MB space (due to TLB pinning) so we can
|
||
|
|
* be generous.
|
||
|
|
*/
|
||
|
|
LIB_OBJ_FUNC_IN_SECT(libkernel.a,,*)
|
||
|
|
|
||
|
|
LIB_OBJ_FUNC_IN_SECT(libdrivers__console.a,,*)
|
||
|
|
LIB_OBJ_FUNC_IN_SECT(libdrivers__timer.a,,*)
|
||
|
|
|
||
|
|
*(.literal.z_vrfy_* .text.z_vrfy_*)
|
||
|
|
*(.literal.z_mrsh_* .text.z_mrsh_*)
|
||
|
|
*(.literal.z_impl_* .text.z_impl_*)
|
||
|
|
*(.literal.z_obj_* .text.z_obj_*)
|
||
|
|
|
||
|
|
*(.literal.k_sys_fatal_error_handler .text.k_sys_fatal_error_handler)
|
||
|
|
} >vec_helpers :vec_helpers_phdr
|
||
|
|
#endif /* CONFIG_XTENSA_MPU */
|
||
|
|
|
||
|
|
#ifdef CONFIG_CODE_DATA_RELOCATION
|
||
|
|
#include <linker_relocate.ld>
|
||
|
|
#endif
|
||
|
|
|
||
|
|
.ResetVector.text : ALIGN(4)
|
||
|
|
{
|
||
|
|
__rom_region_start = ABSOLUTE(.);
|
||
|
|
_ResetVector_text_start = ABSOLUTE(.);
|
||
|
|
KEEP (*(.ResetVector.text))
|
||
|
|
_ResetVector_text_end = ABSOLUTE(.);
|
||
|
|
} >srom0_seg :srom0_phdr
|
||
|
|
|
||
|
|
.text : HDR_MPU_SEGMENT_SIZE_ALIGN
|
||
|
|
{
|
||
|
|
_stext = .;
|
||
|
|
__text_region_start = .;
|
||
|
|
z_mapped_start = .;
|
||
|
|
_text_start = ABSOLUTE(.);
|
||
|
|
*(.entry.text)
|
||
|
|
*(.init.literal)
|
||
|
|
*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
|
||
|
|
*(.iram1.literal .iram1)
|
||
|
|
KEEP(*(.init))
|
||
|
|
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
|
||
|
|
*(.fini.literal)
|
||
|
|
KEEP(*(.fini))
|
||
|
|
*(.gnu.version)
|
||
|
|
|
||
|
|
#include <zephyr/linker/kobject-text.ld>
|
||
|
|
|
||
|
|
MPU_SEGMENT_SIZE_ALIGN
|
||
|
|
|
||
|
|
_text_end = ABSOLUTE(.);
|
||
|
|
_etext = .;
|
||
|
|
} >RAMABLE_REGION
|
||
|
|
__text_region_end = .;
|
||
|
|
|
||
|
|
.rodata : HDR_MPU_SEGMENT_SIZE_ALIGN
|
||
|
|
{
|
||
|
|
__rodata_region_start = ABSOLUTE(.);
|
||
|
|
*(.rodata)
|
||
|
|
*(.rodata.*)
|
||
|
|
*(.gnu.linkonce.r.*)
|
||
|
|
*(.rodata1)
|
||
|
|
|
||
|
|
. = ALIGN(4);
|
||
|
|
#include <snippets-rodata.ld>
|
||
|
|
#include <zephyr/linker/kobject-rom.ld>
|
||
|
|
} >RAMABLE_REGION
|
||
|
|
|
||
|
|
#include <zephyr/linker/common-rom.ld>
|
||
|
|
|
||
|
|
#include <zephyr/linker/thread-local-storage.ld>
|
||
|
|
|
||
|
|
#include <zephyr/linker/cplusplus-rom.ld>
|
||
|
|
|
||
|
|
.rodata_end : ALIGN(4)
|
||
|
|
{
|
||
|
|
. = ALIGN(4); /* this table MUST be 4-byte aligned */
|
||
|
|
_bss_table_start = ABSOLUTE(.);
|
||
|
|
LONG(_bss_start)
|
||
|
|
LONG(_bss_end)
|
||
|
|
_bss_table_end = ABSOLUTE(.);
|
||
|
|
|
||
|
|
MPU_SEGMENT_SIZE_ALIGN
|
||
|
|
|
||
|
|
__rodata_region_end = ABSOLUTE(.);
|
||
|
|
} >RAMABLE_REGION
|
||
|
|
|
||
|
|
#ifdef CONFIG_USERSPACE
|
||
|
|
#define SMEM_PARTITION_ALIGN(size) MPU_SEGMENT_SIZE_ALIGN
|
||
|
|
#define APP_SHARED_ALIGN MPU_SEGMENT_SIZE_ALIGN
|
||
|
|
|
||
|
|
#include <app_smem.ld>
|
||
|
|
|
||
|
|
_image_ram_start = _app_smem_start;
|
||
|
|
_app_smem_size = _app_smem_end - _app_smem_start;
|
||
|
|
_app_smem_num_words = _app_smem_size >> 2;
|
||
|
|
_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
|
||
|
|
_app_smem_num_words = _app_smem_size >> 2;
|
||
|
|
#endif /* CONFIG_USERSPACE */
|
||
|
|
|
||
|
|
.data : HDR_MPU_SEGMENT_SIZE_ALIGN
|
||
|
|
{
|
||
|
|
#ifndef CONFIG_USERSPACE
|
||
|
|
_image_ram_start = ABSOLUTE(.);
|
||
|
|
#endif
|
||
|
|
__data_start = ABSOLUTE(.);
|
||
|
|
*(.data)
|
||
|
|
*(.data.*)
|
||
|
|
*(.gnu.linkonce.d.*)
|
||
|
|
KEEP(*(.gnu.linkonce.d.*personality*))
|
||
|
|
*(.data1)
|
||
|
|
*(.sdata)
|
||
|
|
*(.sdata.*)
|
||
|
|
*(.gnu.linkonce.s.*)
|
||
|
|
*(.sdata2)
|
||
|
|
*(.sdata2.*)
|
||
|
|
*(.gnu.linkonce.s2.*)
|
||
|
|
KEEP(*(.jcr))
|
||
|
|
|
||
|
|
. = ALIGN(4);
|
||
|
|
#include <snippets-rwdata.ld>
|
||
|
|
. = ALIGN(4);
|
||
|
|
|
||
|
|
MPU_SEGMENT_SIZE_ALIGN
|
||
|
|
|
||
|
|
__data_end = ABSOLUTE(.);
|
||
|
|
} >RAMABLE_REGION
|
||
|
|
|
||
|
|
#include <snippets-sections.ld>
|
||
|
|
|
||
|
|
#include <snippets-data-sections.ld>
|
||
|
|
|
||
|
|
#include <zephyr/linker/common-ram.ld>
|
||
|
|
|
||
|
|
#include <zephyr/linker/cplusplus-ram.ld>
|
||
|
|
|
||
|
|
#include <snippets-ram-sections.ld>
|
||
|
|
|
||
|
|
.bss (NOLOAD) : HDR_MPU_SEGMENT_SIZE_ALIGN
|
||
|
|
{
|
||
|
|
. = ALIGN (8);
|
||
|
|
_bss_start = ABSOLUTE(.);
|
||
|
|
*(.dynsbss)
|
||
|
|
*(.sbss)
|
||
|
|
*(.sbss.*)
|
||
|
|
*(.gnu.linkonce.sb.*)
|
||
|
|
*(.scommon)
|
||
|
|
*(.sbss2)
|
||
|
|
*(.sbss2.*)
|
||
|
|
*(.gnu.linkonce.sb2.*)
|
||
|
|
*(.dynbss)
|
||
|
|
*(.bss)
|
||
|
|
*(.bss.*)
|
||
|
|
*(.gnu.linkonce.b.*)
|
||
|
|
*(COMMON)
|
||
|
|
*(.sram.bss)
|
||
|
|
. = ALIGN (8);
|
||
|
|
_bss_end = ABSOLUTE(.);
|
||
|
|
|
||
|
|
MPU_SEGMENT_SIZE_ALIGN
|
||
|
|
|
||
|
|
} >RAM :sram0_bss_phdr
|
||
|
|
|
||
|
|
#include <zephyr/linker/common-noinit.ld>
|
||
|
|
|
||
|
|
/* Must be last in RAM */
|
||
|
|
#include <zephyr/linker/kobject-data.ld>
|
||
|
|
|
||
|
|
#include <zephyr/linker/ram-end.ld>
|
||
|
|
|
||
|
|
_heap_start = .;
|
||
|
|
|
||
|
|
PROVIDE(_heap_sentry = ORIGIN(RAM) + LENGTH(RAM));
|
||
|
|
PROVIDE(_heap_end = ORIGIN(RAM) + LENGTH(RAM));
|
||
|
|
|
||
|
|
PROVIDE(__stack = z_interrupt_stacks + CONFIG_ISR_STACK_SIZE);
|
||
|
|
|
||
|
|
#include <zephyr/linker/debug-sections.ld>
|
||
|
|
|
||
|
|
.xtensa.info 0 : { *(.xtensa.info) }
|
||
|
|
.xt.insn 0 :
|
||
|
|
{
|
||
|
|
KEEP (*(.xt.insn))
|
||
|
|
KEEP (*(.gnu.linkonce.x.*))
|
||
|
|
}
|
||
|
|
.xt.prop 0 :
|
||
|
|
{
|
||
|
|
KEEP (*(.xt.prop))
|
||
|
|
KEEP (*(.xt.prop.*))
|
||
|
|
KEEP (*(.gnu.linkonce.prop.*))
|
||
|
|
}
|
||
|
|
.xt.lit 0 :
|
||
|
|
{
|
||
|
|
KEEP (*(.xt.lit))
|
||
|
|
KEEP (*(.xt.lit.*))
|
||
|
|
KEEP (*(.gnu.linkonce.p.*))
|
||
|
|
}
|
||
|
|
.debug.xt.callgraph 0 :
|
||
|
|
{
|
||
|
|
KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
|
||
|
|
}
|
||
|
|
}
|