michaelh/zephyr
1
0
Fork 0
Code Releases Activity
zephyr/arch/x86/core/intel64/thread.c

61 lines
1.6 KiB
C
Raw Normal View History

arch/x86: initial Intel64 bootstrap framework This patch adds basic build infrastructure, definitions, a linker script, etc. to use the Zephyr and 0.10.1 SDK to build a 64-bit ELF binary suitable for use with GRUB to minimally bootstrap an Apollo Lake (e.g., UpSquared) board. The resulting binary can hardly be called a Zephyr kernel as it is lacking most of the glue logic, but it is a starting point to flesh those out in the x86 tree. The "kernel" builds with a few harmless warnings, both with GCC from the Zephyr SDK and with ICC (which is currently being worked on in a separate branch). These warnings are either related to pointer size differences (since this is an LP64 build) and/or dummy functions that will be replaced with working versions shortly. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-04 13:49:06 -07:00
/*
* Copyright (c) 2019 Intel Corporation
* SPDX-License-Identifier: Apache-2.0
*/
arch/x86: initial Intel64 support First "complete" version of Intel64 support for x86. Compilation of apps for supported boards (read: up_squared) with CONFIG_X86_LONGMODE=y is now working. Booting, device drivers, interrupts, scheduling, etc. appear to be functioning properly. Beware that this is ALHPA quality, not ready for production use, but the port has advanced far enough that it's time to start working through the test suite and samples, fleshing out any missing features, and squashing bugs. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-04 20:17:14 -07:00
#include <kernel.h>
#include <ksched.h>
#include <kernel_structs.h>
#include <kernel_internal.h>
x86: implement kernel page table isolation Implement a set of per-cpu trampoline stacks which all interrupts and exceptions will initially land on, and also as an intermediate stack for privilege changes as we need some stack space to swap page tables. Set up the special trampoline page which contains all the trampoline stacks, TSS, and GDT. This page needs to be present in the user page tables or interrupts don't work. CPU exceptions, with KPTI turned on, are treated as interrupts and not traps so that we have IRQs locked on exception entry. Add some additional macros for defining IDT entries. Add special handling of locore text/rodata sections when creating user mode page tables on x86-64. Restore qemu_x86_64 to use KPTI, and remove restrictions on enabling user mode on x86-64. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-12-18 23:57:25 -08:00
#include <offsets_short.h>
arch/x86: initial Intel64 support First "complete" version of Intel64 support for x86. Compilation of apps for supported boards (read: up_squared) with CONFIG_X86_LONGMODE=y is now working. Booting, device drivers, interrupts, scheduling, etc. appear to be functioning properly. Beware that this is ALHPA quality, not ready for production use, but the port has advanced far enough that it's time to start working through the test suite and samples, fleshing out any missing features, and squashing bugs. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-04 20:17:14 -07:00
arch/x86: add SSE floating-point to Intel64 subarch This is a naive implementation which does "eager" context switching for floating-point context, which, of course, introduces performance concerns. Other approaches have security concerns, SMP implications, and impact the x86 arch and Zephyr project as a whole. Discussion is needed, so punting with the straightforward solution for now. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-24 11:40:24 -07:00
extern void x86_sse_init(struct k_thread *); /* in locore.S */
kernel: overhaul stack specification The core kernel computes the initial stack pointer for a thread, properly aligning it and subtracting out any random offsets or thread-local storage areas. arch_new_thread() no longer needs to make any calculations, an initial stack frame may be placed at the bounds of the new 'stack_ptr' parameter passed in. This parameter replaces 'stack_size'. thread->stack_info is now set before arch_new_thread() is invoked, z_new_thread_init() has been removed. The values populated may need to be adjusted on arches which carve-out MPU guard space from the actual stack buffer. thread->stack_info now has a new member 'delta' which indicates any offset applied for TLS or random offset. It's used so the calculations don't need to be repeated if the thread later drops to user mode. CONFIG_INIT_STACKS logic is now performed inside z_setup_new_thread(), before arch_new_thread() is called. thread->stack_info is now defined as the canonical user-accessible area within the stack object, including random offsets and TLS. It will never include any carved-out memory for MPU guards and must be updated at runtime if guards are removed. Available stack space is now optimized. Some arches may need to significantly round up the buffer size to account for page-level granularity or MPU power-of-two requirements. This space is now accounted for and used by virtue of the Z_THREAD_STACK_SIZE_ADJUST() call in z_setup_new_thread. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-04-23 13:55:56 -07:00
struct x86_initial_frame {
/* zeroed return address for ABI */
uint64_t rip;
};
kernel: rename z_arch_ to arch_ Promote the private z_arch_* namespace, which specifies the interface between the core kernel and the architecture code, to a new top-level namespace named arch_*. This allows our documentation generation to create online documentation for this set of interfaces, and this set of interfaces is worth treating in a more formal way anyway. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-11-07 12:43:29 -08:00
void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
kernel: overhaul stack specification The core kernel computes the initial stack pointer for a thread, properly aligning it and subtracting out any random offsets or thread-local storage areas. arch_new_thread() no longer needs to make any calculations, an initial stack frame may be placed at the bounds of the new 'stack_ptr' parameter passed in. This parameter replaces 'stack_size'. thread->stack_info is now set before arch_new_thread() is invoked, z_new_thread_init() has been removed. The values populated may need to be adjusted on arches which carve-out MPU guard space from the actual stack buffer. thread->stack_info now has a new member 'delta' which indicates any offset applied for TLS or random offset. It's used so the calculations don't need to be repeated if the thread later drops to user mode. CONFIG_INIT_STACKS logic is now performed inside z_setup_new_thread(), before arch_new_thread() is called. thread->stack_info is now defined as the canonical user-accessible area within the stack object, including random offsets and TLS. It will never include any carved-out memory for MPU guards and must be updated at runtime if guards are removed. Available stack space is now optimized. Some arches may need to significantly round up the buffer size to account for page-level granularity or MPU power-of-two requirements. This space is now accounted for and used by virtue of the Z_THREAD_STACK_SIZE_ADJUST() call in z_setup_new_thread. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-04-23 13:55:56 -07:00
char *stack_ptr, k_thread_entry_t entry,
arches: fix arch_new_thread param names MISRA-C wants the parameter names in a function implementaion to match the names used by the header prototype. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-04-23 11:32:08 -07:00
void *p1, void *p2, void *p3)
arch/x86: initial Intel64 bootstrap framework This patch adds basic build infrastructure, definitions, a linker script, etc. to use the Zephyr and 0.10.1 SDK to build a 64-bit ELF binary suitable for use with GRUB to minimally bootstrap an Apollo Lake (e.g., UpSquared) board. The resulting binary can hardly be called a Zephyr kernel as it is lacking most of the glue logic, but it is a starting point to flesh those out in the x86 tree. The "kernel" builds with a few harmless warnings, both with GCC from the Zephyr SDK and with ICC (which is currently being worked on in a separate branch). These warnings are either related to pointer size differences (since this is an LP64 build) and/or dummy functions that will be replaced with working versions shortly. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-04 13:49:06 -07:00
{
x86: implement user mode on 64-bit - In early boot, enable the syscall instruction and set up necessary MSRs - Add a hook to update page tables on context switch - Properly initialize thread based on whether it will start in user or supervisor mode - Add landing function for system calls to execute the desired handler - Implement arch_user_string_nlen() - Implement logic for dropping a thread down to user mode - Reserve per-CPU storage space for user and privilege elevation stack pointers, necessary for handling syscalls when no free registers are available - Proper handling of gs register considerations when transitioning privilege levels Kernel page table isolation (KPTI) is not yet implemented. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-12-18 14:30:41 -08:00
void *switch_entry;
kernel: overhaul stack specification The core kernel computes the initial stack pointer for a thread, properly aligning it and subtracting out any random offsets or thread-local storage areas. arch_new_thread() no longer needs to make any calculations, an initial stack frame may be placed at the bounds of the new 'stack_ptr' parameter passed in. This parameter replaces 'stack_size'. thread->stack_info is now set before arch_new_thread() is invoked, z_new_thread_init() has been removed. The values populated may need to be adjusted on arches which carve-out MPU guard space from the actual stack buffer. thread->stack_info now has a new member 'delta' which indicates any offset applied for TLS or random offset. It's used so the calculations don't need to be repeated if the thread later drops to user mode. CONFIG_INIT_STACKS logic is now performed inside z_setup_new_thread(), before arch_new_thread() is called. thread->stack_info is now defined as the canonical user-accessible area within the stack object, including random offsets and TLS. It will never include any carved-out memory for MPU guards and must be updated at runtime if guards are removed. Available stack space is now optimized. Some arches may need to significantly round up the buffer size to account for page-level granularity or MPU power-of-two requirements. This space is now accounted for and used by virtue of the Z_THREAD_STACK_SIZE_ADJUST() call in z_setup_new_thread. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-04-23 13:55:56 -07:00
struct x86_initial_frame *iframe;
arch/x86: initial Intel64 support First "complete" version of Intel64 support for x86. Compilation of apps for supported boards (read: up_squared) with CONFIG_X86_LONGMODE=y is now working. Booting, device drivers, interrupts, scheduling, etc. appear to be functioning properly. Beware that this is ALHPA quality, not ready for production use, but the port has advanced far enough that it's time to start working through the test suite and samples, fleshing out any missing features, and squashing bugs. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-04 20:17:14 -07:00
x86: enable stack overflow detection on 64-bit CONFIG_HW_STACK_PROTECTION is now available. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-11-05 14:00:30 -08:00
#if CONFIG_X86_STACK_PROTECTION
x86: implement user mode on 64-bit - In early boot, enable the syscall instruction and set up necessary MSRs - Add a hook to update page tables on context switch - Properly initialize thread based on whether it will start in user or supervisor mode - Add landing function for system calls to execute the desired handler - Implement arch_user_string_nlen() - Implement logic for dropping a thread down to user mode - Reserve per-CPU storage space for user and privilege elevation stack pointers, necessary for handling syscalls when no free registers are available - Proper handling of gs register considerations when transitioning privilege levels Kernel page table isolation (KPTI) is not yet implemented. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-12-18 14:30:41 -08:00
struct z_x86_thread_stack_header *header =
(struct z_x86_thread_stack_header *)stack;
x86: enable stack overflow detection on 64-bit CONFIG_HW_STACK_PROTECTION is now available. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-11-05 14:00:30 -08:00
/* Set guard area to read-only to catch stack overflows */
z_x86_mmu_set_flags(&z_x86_kernel_ptables, &header->guard_page,
MMU_PAGE_SIZE, MMU_ENTRY_READ, Z_X86_MMU_RW,
true);
#endif
x86: implement user mode on 64-bit - In early boot, enable the syscall instruction and set up necessary MSRs - Add a hook to update page tables on context switch - Properly initialize thread based on whether it will start in user or supervisor mode - Add landing function for system calls to execute the desired handler - Implement arch_user_string_nlen() - Implement logic for dropping a thread down to user mode - Reserve per-CPU storage space for user and privilege elevation stack pointers, necessary for handling syscalls when no free registers are available - Proper handling of gs register considerations when transitioning privilege levels Kernel page table isolation (KPTI) is not yet implemented. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-12-18 14:30:41 -08:00
#ifdef CONFIG_USERSPACE
switch_entry = z_x86_userspace_prepare_thread(thread);
thread->arch.cs = X86_KERNEL_CS;
thread->arch.ss = X86_KERNEL_DS;
#else
switch_entry = z_thread_entry;
#endif
kernel: overhaul stack specification The core kernel computes the initial stack pointer for a thread, properly aligning it and subtracting out any random offsets or thread-local storage areas. arch_new_thread() no longer needs to make any calculations, an initial stack frame may be placed at the bounds of the new 'stack_ptr' parameter passed in. This parameter replaces 'stack_size'. thread->stack_info is now set before arch_new_thread() is invoked, z_new_thread_init() has been removed. The values populated may need to be adjusted on arches which carve-out MPU guard space from the actual stack buffer. thread->stack_info now has a new member 'delta' which indicates any offset applied for TLS or random offset. It's used so the calculations don't need to be repeated if the thread later drops to user mode. CONFIG_INIT_STACKS logic is now performed inside z_setup_new_thread(), before arch_new_thread() is called. thread->stack_info is now defined as the canonical user-accessible area within the stack object, including random offsets and TLS. It will never include any carved-out memory for MPU guards and must be updated at runtime if guards are removed. Available stack space is now optimized. Some arches may need to significantly round up the buffer size to account for page-level granularity or MPU power-of-two requirements. This space is now accounted for and used by virtue of the Z_THREAD_STACK_SIZE_ADJUST() call in z_setup_new_thread. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-04-23 13:55:56 -07:00
iframe = Z_STACK_PTR_TO_FRAME(struct x86_initial_frame, stack_ptr);
iframe->rip = 0;
thread->callee_saved.rsp = (long) iframe;
x86: implement user mode on 64-bit - In early boot, enable the syscall instruction and set up necessary MSRs - Add a hook to update page tables on context switch - Properly initialize thread based on whether it will start in user or supervisor mode - Add landing function for system calls to execute the desired handler - Implement arch_user_string_nlen() - Implement logic for dropping a thread down to user mode - Reserve per-CPU storage space for user and privilege elevation stack pointers, necessary for handling syscalls when no free registers are available - Proper handling of gs register considerations when transitioning privilege levels Kernel page table isolation (KPTI) is not yet implemented. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-12-18 14:30:41 -08:00
thread->callee_saved.rip = (long) switch_entry;
arch/x86: initial Intel64 support First "complete" version of Intel64 support for x86. Compilation of apps for supported boards (read: up_squared) with CONFIG_X86_LONGMODE=y is now working. Booting, device drivers, interrupts, scheduling, etc. appear to be functioning properly. Beware that this is ALHPA quality, not ready for production use, but the port has advanced far enough that it's time to start working through the test suite and samples, fleshing out any missing features, and squashing bugs. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-04 20:17:14 -07:00
thread->callee_saved.rflags = EFLAGS_INITIAL;
x86: implement user mode on 64-bit - In early boot, enable the syscall instruction and set up necessary MSRs - Add a hook to update page tables on context switch - Properly initialize thread based on whether it will start in user or supervisor mode - Add landing function for system calls to execute the desired handler - Implement arch_user_string_nlen() - Implement logic for dropping a thread down to user mode - Reserve per-CPU storage space for user and privilege elevation stack pointers, necessary for handling syscalls when no free registers are available - Proper handling of gs register considerations when transitioning privilege levels Kernel page table isolation (KPTI) is not yet implemented. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-12-18 14:30:41 -08:00
/* Parameters to entry point, which is populated in
* thread->callee_saved.rip
*/
arch/x86: initial Intel64 support First "complete" version of Intel64 support for x86. Compilation of apps for supported boards (read: up_squared) with CONFIG_X86_LONGMODE=y is now working. Booting, device drivers, interrupts, scheduling, etc. appear to be functioning properly. Beware that this is ALHPA quality, not ready for production use, but the port has advanced far enough that it's time to start working through the test suite and samples, fleshing out any missing features, and squashing bugs. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-04 20:17:14 -07:00
thread->arch.rdi = (long) entry;
arches: fix arch_new_thread param names MISRA-C wants the parameter names in a function implementaion to match the names used by the header prototype. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-04-23 11:32:08 -07:00
thread->arch.rsi = (long) p1;
thread->arch.rdx = (long) p2;
thread->arch.rcx = (long) p3;
arch/x86: add SSE floating-point to Intel64 subarch This is a naive implementation which does "eager" context switching for floating-point context, which, of course, introduces performance concerns. Other approaches have security concerns, SMP implications, and impact the x86 arch and Zephyr project as a whole. Discussion is needed, so punting with the straightforward solution for now. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-24 11:40:24 -07:00
x86_sse_init(thread);
arch/x86/intel64: do not use thread_state for arch data k_thread.thread_state (or rather, _thread_base.thread_state) should be private to the kernel/scheduler, so flags previously stored there are moved to _thread_arch where the belong. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-18 17:55:25 -04:00
thread->arch.flags = X86_THREAD_FLAG_ALL;
arch/x86: (Intel64) migrate from __swap to z_arch_switch() The latter primitive is required for SMP. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-23 13:57:12 -04:00
thread->switch_handle = thread;
arch/x86: initial Intel64 bootstrap framework This patch adds basic build infrastructure, definitions, a linker script, etc. to use the Zephyr and 0.10.1 SDK to build a 64-bit ELF binary suitable for use with GRUB to minimally bootstrap an Apollo Lake (e.g., UpSquared) board. The resulting binary can hardly be called a Zephyr kernel as it is lacking most of the glue logic, but it is a starting point to flesh those out in the x86 tree. The "kernel" builds with a few harmless warnings, both with GCC from the Zephyr SDK and with ICC (which is currently being worked on in a separate branch). These warnings are either related to pointer size differences (since this is an LP64 build) and/or dummy functions that will be replaced with working versions shortly. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-04 13:49:06 -07:00
}
Copy permalink