129 lines
3.5 KiB
C
129 lines
3.5 KiB
C
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/*
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* Copyright 2024 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/device.h>
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#include <fsl_clock.h>
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#include <fsl_spc.h>
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/* Board xtal frequency in Hz */
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#define BOARD_XTAL0_CLK_HZ 24000000U
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/* Core clock frequency: 150MHz */
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#define CLOCK_INIT_CORE_CLOCK 150000000U
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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__ramfunc static void enable_lpcac(void)
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{
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SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK;
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SYSCON->LPCAC_CTRL &= ~(SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK |
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SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK);
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}
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/* Update Active mode voltage for OverDrive mode. */
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void power_mode_od(void)
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{
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/* Set the DCDC VDD regulator to 1.2 V voltage level */
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spc_active_mode_dcdc_option_t opt = {
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.DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
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.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
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};
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SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt);
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/* Set the LDO_CORE VDD regulator to 1.2 V voltage level */
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spc_active_mode_core_ldo_option_t ldo_opt = {
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.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage,
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.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
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};
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SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_opt);
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/* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */
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spc_sram_voltage_config_t cfg = {
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.operateVoltage = kSPC_sramOperateAt1P2V,
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.requestVoltageUpdate = true,
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};
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SPC_SetSRAMOperateVoltage(SPC0, &cfg);
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}
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static int frdm_mcxn947_init(void)
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{
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enable_lpcac();
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power_mode_od();
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/* Enable SCG clock */
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CLOCK_EnableClock(kCLOCK_Scg);
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/* FRO OSC setup - begin, enable the FRO for safety switching */
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/* Switch to FRO 12M first to ensure we can change the clock setting */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
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/* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */
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FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U));
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/* Enable FRO HF(48MHz) output */
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CLOCK_SetupFROHFClocking(48000000U);
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/* Set up PLL0 */
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const pll_setup_t pll0Setup = {
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.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) |
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SCG_APLLCTRL_SELP(13U),
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.pllndiv = SCG_APLLNDIV_NDIV(8U),
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.pllpdiv = SCG_APLLPDIV_PDIV(1U),
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.pllmdiv = SCG_APLLMDIV_MDIV(50U),
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.pllRate = 150000000U
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};
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/* Configure PLL0 to the desired values */
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CLOCK_SetPLL0Freq(&pll0Setup);
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/* PLL0 Monitor is disabled */
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CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);
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/* Switch MAIN_CLK to PLL0 */
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CLOCK_AttachClk(kPLL0_to_MAIN_CLK);
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/* Set AHBCLKDIV divider to value 1 */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay)
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CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
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CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(os_timer), okay)
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CLOCK_AttachClk(kCLK_1M_to_OSTIMER);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
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CLOCK_EnableClock(kCLOCK_Gpio0);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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CLOCK_EnableClock(kCLOCK_Gpio1);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
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CLOCK_EnableClock(kCLOCK_Gpio2);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
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CLOCK_EnableClock(kCLOCK_Gpio3);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
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CLOCK_EnableClock(kCLOCK_Gpio4);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
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CLOCK_EnableClock(kCLOCK_Gpio5);
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#endif
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/* Set SystemCoreClock variable. */
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SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
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return 0;
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}
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SYS_INIT(frdm_mcxn947_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
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