2020-10-02 14:29:47 +02:00
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/*
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2021-10-07 11:21:51 +05:30
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* Copyright (c) 2021 Nordic Semiconductor ASA
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2020-10-02 14:29:47 +02:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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includes: prefer <zephyr/kernel.h> over <zephyr/zephyr.h>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.
The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.
NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-25 09:58:46 +02:00
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#include <zephyr/kernel.h>
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2021-10-07 11:21:51 +05:30
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#include <soc.h>
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2022-05-06 11:12:04 +02:00
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#include <zephyr/sys/byteorder.h>
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#include <zephyr/bluetooth/bluetooth.h>
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2020-10-02 14:29:47 +02:00
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2020-10-21 21:14:07 +02:00
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#include "hal/cpu.h"
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2020-10-30 11:26:26 +01:00
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#include "hal/ccm.h"
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#include "hal/ticker.h"
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2020-10-21 21:14:07 +02:00
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#include "util/util.h"
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2020-10-30 11:26:26 +01:00
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#include "util/mem.h"
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2021-02-24 16:42:02 +05:30
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#include "util/memq.h"
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2020-10-30 11:26:26 +01:00
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#include "util/mfifo.h"
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2021-02-24 16:42:02 +05:30
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#include "util/mayfly.h"
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2020-10-30 11:26:26 +01:00
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#include "ticker/ticker.h"
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2020-10-21 21:14:07 +02:00
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#include "pdu.h"
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2021-02-24 16:42:02 +05:30
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#include "lll.h"
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#include "lll/lll_vendor.h"
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#include "lll/lll_adv_types.h"
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2020-10-21 21:14:07 +02:00
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#include "lll_adv.h"
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2021-02-24 16:42:02 +05:30
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#include "lll/lll_adv_pdu.h"
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2021-01-18 17:13:52 +05:30
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#include "lll_adv_iso.h"
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2022-05-25 09:58:17 +05:30
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#include "lll_iso_tx.h"
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2020-10-21 21:14:07 +02:00
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#include "ull_adv_types.h"
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2022-01-19 20:57:50 +05:30
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#include "ull_internal.h"
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2020-10-21 21:14:07 +02:00
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#include "ull_adv_internal.h"
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2021-01-15 17:08:16 +05:30
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#include "ull_chan_internal.h"
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2022-02-18 06:20:56 +05:30
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#include "ull_sched_internal.h"
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2020-10-21 21:14:07 +02:00
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2021-02-24 16:42:02 +05:30
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#include "ll.h"
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2021-03-16 13:31:26 +05:30
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#include "ll_feat.h"
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2021-02-24 16:42:02 +05:30
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#define BT_DBG_ENABLED IS_ENABLED(CONFIG_BT_DEBUG_HCI_DRIVER)
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#define LOG_MODULE_NAME bt_ctlr_ull_adv_iso
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#include "common/log.h"
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#include "hal/debug.h"
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2021-11-23 21:34:04 +05:30
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static int init_reset(void);
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static struct ll_adv_iso_set *adv_iso_get(uint8_t handle);
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static struct stream *adv_iso_stream_acquire(void);
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static uint16_t adv_iso_stream_handle_get(struct lll_adv_iso_stream *stream);
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static uint8_t ptc_calc(const struct lll_adv_iso *lll, uint32_t latency_pdu,
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uint32_t latency_packing, uint32_t ctrl_spacing);
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static uint32_t adv_iso_start(struct ll_adv_iso_set *adv_iso,
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2022-02-18 06:20:56 +05:30
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uint32_t iso_interval_us);
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2022-01-19 20:57:50 +05:30
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static uint8_t adv_iso_chm_update(uint8_t big_handle);
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static void adv_iso_chm_complete_commit(struct lll_adv_iso *lll_iso);
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2021-01-18 17:13:52 +05:30
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static void mfy_iso_offset_get(void *param);
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2022-01-19 20:57:50 +05:30
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static void pdu_big_info_chan_map_phy_set(uint8_t *chm_phy, uint8_t *chan_map,
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uint8_t phy);
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2021-01-18 17:13:52 +05:30
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static inline struct pdu_big_info *big_info_get(struct pdu_adv *pdu);
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static inline void big_info_offset_fill(struct pdu_big_info *bi,
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uint32_t ticks_offset,
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uint32_t start_us);
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2021-09-15 11:48:21 +05:30
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static void ticker_cb(uint32_t ticks_at_expire, uint32_t ticks_drift,
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uint32_t remainder, uint16_t lazy, uint8_t force,
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void *param);
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2021-01-18 17:13:52 +05:30
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static void ticker_op_cb(uint32_t status, void *param);
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2021-08-17 14:34:39 +05:30
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static void ticker_stop_op_cb(uint32_t status, void *param);
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2021-08-16 16:50:07 +05:30
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static void adv_iso_disable(void *param);
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2021-04-15 11:24:21 +05:30
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static void disabled_cb(void *param);
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static void tx_lll_flush(void *param);
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2020-11-26 14:03:27 +01:00
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2021-01-19 16:04:51 +05:30
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static memq_link_t link_lll_prepare;
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2021-11-16 13:04:21 +05:30
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static struct mayfly mfy_lll_prepare = {0U, 0U, &link_lll_prepare, NULL, NULL};
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2021-01-19 16:04:51 +05:30
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2021-11-23 21:34:04 +05:30
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static struct ll_adv_iso_set ll_adv_iso[CONFIG_BT_CTLR_ADV_ISO_SET];
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static struct lll_adv_iso_stream
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stream_pool[CONFIG_BT_CTLR_ADV_ISO_STREAM_COUNT];
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static void *stream_free;
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2021-02-18 13:02:24 +05:30
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2020-11-26 14:03:27 +01:00
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uint8_t ll_big_create(uint8_t big_handle, uint8_t adv_handle, uint8_t num_bis,
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uint32_t sdu_interval, uint16_t max_sdu,
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uint16_t max_latency, uint8_t rtn, uint8_t phy,
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uint8_t packing, uint8_t framing, uint8_t encryption,
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2020-12-01 15:38:13 +01:00
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uint8_t *bcode)
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2020-10-30 11:26:26 +01:00
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{
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2021-07-15 07:57:04 +02:00
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uint8_t hdr_data[1 + sizeof(uint8_t *)];
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2021-01-04 13:22:23 +05:30
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struct lll_adv_sync *lll_adv_sync;
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struct lll_adv_iso *lll_adv_iso;
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2021-01-06 13:32:08 +05:30
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struct ll_adv_iso_set *adv_iso;
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2021-02-24 12:39:57 +05:30
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struct pdu_adv *pdu_prev, *pdu;
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2021-01-15 17:08:16 +05:30
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struct pdu_big_info *big_info;
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uint8_t pdu_big_info_size;
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2021-03-16 13:31:26 +05:30
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uint32_t iso_interval_us;
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2022-04-22 18:22:49 +05:30
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uint32_t latency_packing;
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2021-03-10 06:57:56 +05:30
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memq_link_t *link_cmplt;
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memq_link_t *link_term;
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2020-11-26 14:03:27 +01:00
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struct ll_adv_set *adv;
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2021-04-16 11:03:49 +05:30
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uint16_t ctrl_spacing;
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2021-11-16 13:04:21 +05:30
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uint32_t latency_pdu;
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2021-02-24 12:39:57 +05:30
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uint8_t ter_idx;
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2021-01-04 13:27:38 +05:30
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uint8_t *acad;
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2021-01-19 16:04:51 +05:30
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uint32_t ret;
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2021-01-04 13:27:38 +05:30
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uint8_t err;
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2021-03-16 13:31:26 +05:30
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uint8_t bn;
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2020-10-30 11:26:26 +01:00
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2021-11-19 17:04:34 +05:30
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adv_iso = adv_iso_get(big_handle);
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2020-10-30 11:26:26 +01:00
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2021-02-22 13:36:43 +05:30
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/* Already created */
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if (!adv_iso || adv_iso->lll.adv) {
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2020-11-26 14:03:27 +01:00
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return BT_HCI_ERR_CMD_DISALLOWED;
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}
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2021-02-22 13:36:43 +05:30
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/* No advertising set created */
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2020-11-26 14:03:27 +01:00
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adv = ull_adv_is_created_get(adv_handle);
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2021-02-22 13:36:43 +05:30
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if (!adv) {
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return BT_HCI_ERR_UNKNOWN_ADV_IDENTIFIER;
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}
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2020-11-26 14:03:27 +01:00
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2020-12-01 15:13:33 +01:00
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/* Does not identify a periodic advertising train or
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* the periodic advertising trains is already associated
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* with another BIG.
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*/
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2021-01-04 13:22:23 +05:30
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lll_adv_sync = adv->lll.sync;
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2021-02-22 13:36:43 +05:30
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if (!lll_adv_sync || lll_adv_sync->iso) {
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2020-11-26 14:03:27 +01:00
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return BT_HCI_ERR_UNKNOWN_ADV_IDENTIFIER;
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}
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if (IS_ENABLED(CONFIG_BT_CTLR_PARAM_CHECK)) {
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2021-11-16 13:04:21 +05:30
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if (num_bis == 0U || num_bis > 0x1F) {
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2020-11-26 14:03:27 +01:00
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return BT_HCI_ERR_INVALID_PARAM;
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}
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if (sdu_interval < 0x000100 || sdu_interval > 0x0FFFFF) {
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return BT_HCI_ERR_INVALID_PARAM;
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}
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if (max_sdu < 0x0001 || max_sdu > 0x0FFF) {
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return BT_HCI_ERR_INVALID_PARAM;
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}
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if (max_latency > 0x0FA0) {
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return BT_HCI_ERR_INVALID_PARAM;
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}
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if (rtn > 0x0F) {
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return BT_HCI_ERR_INVALID_PARAM;
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}
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if (phy > (BT_HCI_LE_EXT_SCAN_PHY_1M |
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BT_HCI_LE_EXT_SCAN_PHY_2M |
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BT_HCI_LE_EXT_SCAN_PHY_CODED)) {
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return BT_HCI_ERR_INVALID_PARAM;
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}
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2021-11-16 13:04:21 +05:30
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if (packing > 1U) {
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2020-11-26 14:03:27 +01:00
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return BT_HCI_ERR_INVALID_PARAM;
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}
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2021-11-16 13:04:21 +05:30
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if (framing > 1U) {
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2020-11-26 14:03:27 +01:00
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return BT_HCI_ERR_INVALID_PARAM;
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}
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2021-11-16 13:04:21 +05:30
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if (encryption > 1U) {
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2020-11-26 14:03:27 +01:00
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return BT_HCI_ERR_INVALID_PARAM;
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2020-10-30 11:26:26 +01:00
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}
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}
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2021-11-23 21:34:04 +05:30
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/* Check if free BISes available */
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if (mem_free_count_get(stream_free) < num_bis) {
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return BT_HCI_ERR_MEM_CAPACITY_EXCEEDED;
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}
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2021-03-16 13:31:26 +05:30
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/* Allocate link buffer for created event */
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2021-03-10 06:57:56 +05:30
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link_cmplt = ll_rx_link_alloc();
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if (!link_cmplt) {
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return BT_HCI_ERR_MEM_CAPACITY_EXCEEDED;
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}
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2021-03-16 13:31:26 +05:30
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/* Allocate link buffer for sync lost event */
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2021-03-10 06:57:56 +05:30
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link_term = ll_rx_link_alloc();
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if (!link_term) {
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ll_rx_link_release(link_cmplt);
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2021-01-19 16:04:51 +05:30
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return BT_HCI_ERR_MEM_CAPACITY_EXCEEDED;
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}
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2021-04-16 11:03:49 +05:30
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/* Store parameters in LLL context */
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/* TODO: parameters to ULL if only accessed by ULL */
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lll_adv_iso = &adv_iso->lll;
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lll_adv_iso->handle = big_handle;
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2022-09-18 07:08:18 +05:30
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lll_adv_iso->max_pdu = MIN(LL_BIS_OCTETS_TX_MAX, max_sdu);
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2021-08-18 11:53:36 +05:30
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lll_adv_iso->phy = phy;
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2021-08-18 11:41:13 +05:30
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lll_adv_iso->phy_flags = PHY_FLAGS_S8;
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2021-04-16 11:03:49 +05:30
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/* Mandatory Num_BIS = 1 */
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lll_adv_iso->num_bis = num_bis;
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2021-11-23 21:34:04 +05:30
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/* Allocate streams */
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for (uint8_t i = 0U; i < num_bis; i++) {
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struct lll_adv_iso_stream *stream;
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stream = (void *)adv_iso_stream_acquire();
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stream->big_handle = big_handle;
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2021-12-07 13:04:34 +05:30
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if (!stream->link_tx_free) {
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stream->link_tx_free = &stream->link_tx;
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}
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memq_init(stream->link_tx_free, &stream->memq_tx.head,
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&stream->memq_tx.tail);
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stream->link_tx_free = NULL;
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stream->pkt_seq_num = 0U;
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2021-11-23 21:34:04 +05:30
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lll_adv_iso->stream_handle[i] =
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adv_iso_stream_handle_get(stream);
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}
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2021-04-16 11:03:49 +05:30
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/* BN (Burst Count), Mandatory BN = 1 */
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2021-11-17 10:55:13 +05:30
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bn = ceiling_fraction(max_sdu, lll_adv_iso->max_pdu);
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2021-04-16 11:03:49 +05:30
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if (bn > PDU_BIG_BN_MAX) {
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2021-11-16 13:04:21 +05:30
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/* Restrict each BIG event to maximum burst per BIG event */
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2021-04-16 11:03:49 +05:30
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lll_adv_iso->bn = PDU_BIG_BN_MAX;
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2021-11-16 13:04:21 +05:30
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/* Ceil the required burst count per SDU to next maximum burst
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* per BIG event.
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*/
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2021-11-17 10:55:13 +05:30
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bn = ceiling_fraction(bn, PDU_BIG_BN_MAX) * PDU_BIG_BN_MAX;
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2021-04-16 11:03:49 +05:30
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} else {
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lll_adv_iso->bn = bn;
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}
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/* Immediate Repetition Count (IRC), Mandatory IRC = 1 */
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2021-11-16 13:04:21 +05:30
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lll_adv_iso->irc = rtn + 1U;
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2021-03-16 13:31:26 +05:30
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/* Calculate NSE (No. of Sub Events), Mandatory NSE = 1,
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* without PTO added.
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2021-01-15 17:08:16 +05:30
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*/
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2021-03-16 13:31:26 +05:30
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lll_adv_iso->nse = lll_adv_iso->bn * lll_adv_iso->irc;
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/* NOTE: Calculate sub_interval, if interleaved then it is Num_BIS x
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2021-01-15 17:08:16 +05:30
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* BIS_Spacing (by BT Spec.)
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* else if sequential, then by our implementation, lets keep it
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* max_tx_time for Max_PDU + tMSS.
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*/
|
2021-08-18 11:53:36 +05:30
|
|
|
lll_adv_iso->sub_interval = PDU_BIS_US(lll_adv_iso->max_pdu, encryption,
|
2021-08-18 11:41:13 +05:30
|
|
|
phy, lll_adv_iso->phy_flags) +
|
2021-08-18 11:53:36 +05:30
|
|
|
EVENT_MSS_US;
|
|
|
|
ctrl_spacing = PDU_BIS_US(sizeof(struct pdu_big_ctrl), encryption, phy,
|
2021-08-18 11:41:13 +05:30
|
|
|
lll_adv_iso->phy_flags) + EVENT_IFS_US;
|
2021-03-09 11:17:51 +05:30
|
|
|
|
2021-11-16 13:04:21 +05:30
|
|
|
latency_pdu = max_latency * USEC_PER_MSEC * lll_adv_iso->bn / bn;
|
2022-04-22 18:22:49 +05:30
|
|
|
latency_packing = lll_adv_iso->sub_interval * lll_adv_iso->nse *
|
|
|
|
lll_adv_iso->num_bis;
|
2022-06-06 09:28:28 +05:30
|
|
|
if (latency_packing > sdu_interval) {
|
|
|
|
/* SDU interval too small to fit the calculated BIG event
|
|
|
|
* timing required for the supplied BIG create parameters.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Release allocated link buffers */
|
|
|
|
ll_rx_link_release(link_cmplt);
|
|
|
|
ll_rx_link_release(link_term);
|
|
|
|
|
|
|
|
return BT_HCI_ERR_INVALID_PARAM;
|
|
|
|
}
|
2021-04-16 11:03:49 +05:30
|
|
|
|
2021-03-16 13:31:26 +05:30
|
|
|
/* Based on packing requested, sequential or interleaved */
|
|
|
|
if (packing) {
|
|
|
|
lll_adv_iso->bis_spacing = lll_adv_iso->sub_interval;
|
2021-11-19 17:02:13 +05:30
|
|
|
lll_adv_iso->ptc = ptc_calc(lll_adv_iso, latency_pdu,
|
|
|
|
latency_packing, ctrl_spacing);
|
2021-04-16 11:03:49 +05:30
|
|
|
lll_adv_iso->nse += lll_adv_iso->ptc;
|
2021-03-16 13:31:26 +05:30
|
|
|
lll_adv_iso->sub_interval = lll_adv_iso->bis_spacing *
|
|
|
|
lll_adv_iso->nse;
|
|
|
|
} else {
|
2021-11-19 17:02:13 +05:30
|
|
|
lll_adv_iso->ptc = ptc_calc(lll_adv_iso, latency_pdu,
|
|
|
|
latency_packing, ctrl_spacing);
|
2021-04-16 11:03:49 +05:30
|
|
|
lll_adv_iso->nse += lll_adv_iso->ptc;
|
2021-03-16 13:31:26 +05:30
|
|
|
lll_adv_iso->bis_spacing = lll_adv_iso->sub_interval *
|
|
|
|
lll_adv_iso->nse;
|
|
|
|
}
|
|
|
|
|
2021-04-16 11:03:49 +05:30
|
|
|
/* Pre-Transmission Offset (PTO) */
|
|
|
|
if (lll_adv_iso->ptc) {
|
|
|
|
lll_adv_iso->pto = bn / lll_adv_iso->bn;
|
|
|
|
} else {
|
|
|
|
lll_adv_iso->pto = 0U;
|
|
|
|
}
|
|
|
|
|
2021-03-16 13:31:26 +05:30
|
|
|
/* TODO: Group count, GC = NSE / BN; PTO = GC - IRC;
|
|
|
|
* Is this required?
|
|
|
|
*/
|
2021-03-09 11:17:51 +05:30
|
|
|
|
2021-01-15 17:08:16 +05:30
|
|
|
lll_adv_iso->sdu_interval = sdu_interval;
|
|
|
|
lll_adv_iso->max_sdu = max_sdu;
|
2021-03-16 13:31:26 +05:30
|
|
|
|
|
|
|
util_saa_le32(lll_adv_iso->seed_access_addr, big_handle);
|
|
|
|
|
2021-01-15 17:08:16 +05:30
|
|
|
lll_csrand_get(lll_adv_iso->base_crc_init,
|
|
|
|
sizeof(lll_adv_iso->base_crc_init));
|
|
|
|
lll_adv_iso->data_chan_count =
|
|
|
|
ull_chan_map_get(lll_adv_iso->data_chan_map);
|
2021-04-16 11:03:49 +05:30
|
|
|
lll_adv_iso->latency_prepare = 0U;
|
|
|
|
lll_adv_iso->latency_event = 0U;
|
2021-03-16 13:31:26 +05:30
|
|
|
lll_adv_iso->term_req = 0U;
|
|
|
|
lll_adv_iso->term_ack = 0U;
|
|
|
|
lll_adv_iso->chm_req = 0U;
|
|
|
|
lll_adv_iso->chm_ack = 0U;
|
|
|
|
lll_adv_iso->ctrl_expire = 0U;
|
2021-01-15 17:08:16 +05:30
|
|
|
|
|
|
|
/* TODO: framing support */
|
2021-03-07 10:22:45 +05:30
|
|
|
lll_adv_iso->framing = framing;
|
2021-01-15 17:08:16 +05:30
|
|
|
|
2021-03-16 13:31:26 +05:30
|
|
|
/* Calculate ISO interval */
|
|
|
|
/* iso_interval shall be at least SDU interval,
|
|
|
|
* or integer multiple of SDU interval for unframed PDUs
|
|
|
|
*/
|
2021-04-16 11:03:49 +05:30
|
|
|
iso_interval_us = ((sdu_interval * lll_adv_iso->bn) /
|
2022-02-16 11:00:11 +05:30
|
|
|
(bn * PERIODIC_INT_UNIT_US)) * PERIODIC_INT_UNIT_US;
|
2021-01-04 13:27:38 +05:30
|
|
|
|
2021-02-24 12:39:57 +05:30
|
|
|
/* Allocate next PDU */
|
2022-01-19 20:57:50 +05:30
|
|
|
err = ull_adv_sync_pdu_alloc(adv, ULL_ADV_PDU_EXTRA_DATA_ALLOC_IF_EXIST,
|
|
|
|
&pdu_prev, &pdu, NULL, NULL, &ter_idx);
|
2021-02-24 12:39:57 +05:30
|
|
|
if (err) {
|
2022-06-06 09:28:28 +05:30
|
|
|
/* Insufficient Advertising PDU buffers to allocate new PDU
|
|
|
|
* to add BIGInfo into the ACAD of the Periodic Advertising.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Release allocated link buffers */
|
|
|
|
ll_rx_link_release(link_cmplt);
|
|
|
|
ll_rx_link_release(link_term);
|
|
|
|
|
2021-02-24 12:39:57 +05:30
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2021-01-04 13:27:38 +05:30
|
|
|
/* Add ACAD to AUX_SYNC_IND */
|
2021-01-15 17:08:16 +05:30
|
|
|
if (encryption) {
|
|
|
|
pdu_big_info_size = PDU_BIG_INFO_ENCRYPTED_SIZE;
|
|
|
|
} else {
|
|
|
|
pdu_big_info_size = PDU_BIG_INFO_CLEARTEXT_SIZE;
|
|
|
|
}
|
2021-11-16 12:45:40 +05:30
|
|
|
hdr_data[0] = pdu_big_info_size + PDU_ADV_DATA_HEADER_SIZE;
|
2021-01-15 17:08:16 +05:30
|
|
|
err = ull_adv_sync_pdu_set_clear(lll_adv_sync, pdu_prev, pdu,
|
|
|
|
ULL_ADV_PDU_HDR_FIELD_ACAD, 0U,
|
|
|
|
&hdr_data);
|
2021-01-04 13:27:38 +05:30
|
|
|
if (err) {
|
2022-06-06 09:28:28 +05:30
|
|
|
/* Failed to add BIGInfo into the ACAD of the Periodic
|
|
|
|
* Advertising.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Release allocated link buffers */
|
2021-03-10 06:57:56 +05:30
|
|
|
ll_rx_link_release(link_cmplt);
|
|
|
|
ll_rx_link_release(link_term);
|
2021-01-19 16:04:51 +05:30
|
|
|
|
2021-01-04 13:27:38 +05:30
|
|
|
return err;
|
|
|
|
}
|
2021-02-24 12:39:57 +05:30
|
|
|
|
2021-11-16 12:45:40 +05:30
|
|
|
(void)memcpy(&acad, &hdr_data[1], sizeof(acad));
|
|
|
|
acad[PDU_ADV_DATA_HEADER_LEN_OFFSET] =
|
|
|
|
pdu_big_info_size + (PDU_ADV_DATA_HEADER_SIZE -
|
|
|
|
PDU_ADV_DATA_HEADER_LEN_SIZE);
|
|
|
|
acad[PDU_ADV_DATA_HEADER_TYPE_OFFSET] = BT_DATA_BIG_INFO;
|
|
|
|
big_info = (void *)&acad[PDU_ADV_DATA_HEADER_DATA_OFFSET];
|
2021-01-15 17:08:16 +05:30
|
|
|
|
2021-03-16 13:31:26 +05:30
|
|
|
/* big_info->offset, big_info->offset_units and
|
|
|
|
* big_info->payload_count_framing[] will be filled by periodic
|
|
|
|
* advertising event.
|
2021-01-15 17:08:16 +05:30
|
|
|
*/
|
|
|
|
|
2021-11-16 13:00:47 +05:30
|
|
|
big_info->iso_interval =
|
2022-02-16 11:00:11 +05:30
|
|
|
sys_cpu_to_le16(iso_interval_us / PERIODIC_INT_UNIT_US);
|
2021-01-15 17:08:16 +05:30
|
|
|
big_info->num_bis = lll_adv_iso->num_bis;
|
|
|
|
big_info->nse = lll_adv_iso->nse;
|
|
|
|
big_info->bn = lll_adv_iso->bn;
|
2021-11-16 13:00:47 +05:30
|
|
|
big_info->sub_interval = sys_cpu_to_le24(lll_adv_iso->sub_interval);
|
2021-01-15 17:08:16 +05:30
|
|
|
big_info->pto = lll_adv_iso->pto;
|
2021-11-16 13:00:47 +05:30
|
|
|
big_info->spacing = sys_cpu_to_le24(lll_adv_iso->bis_spacing);
|
2021-01-15 17:08:16 +05:30
|
|
|
big_info->irc = lll_adv_iso->irc;
|
|
|
|
big_info->max_pdu = lll_adv_iso->max_pdu;
|
2021-11-16 13:04:21 +05:30
|
|
|
(void)memcpy(&big_info->seed_access_addr, lll_adv_iso->seed_access_addr,
|
|
|
|
sizeof(big_info->seed_access_addr));
|
2021-11-16 13:00:47 +05:30
|
|
|
big_info->sdu_interval = sys_cpu_to_le24(sdu_interval);
|
2021-01-15 17:08:16 +05:30
|
|
|
big_info->max_sdu = max_sdu;
|
2021-11-16 13:04:21 +05:30
|
|
|
(void)memcpy(&big_info->base_crc_init, lll_adv_iso->base_crc_init,
|
|
|
|
sizeof(big_info->base_crc_init));
|
2022-01-19 20:57:50 +05:30
|
|
|
pdu_big_info_chan_map_phy_set(big_info->chm_phy,
|
|
|
|
lll_adv_iso->data_chan_map,
|
|
|
|
phy);
|
2021-03-07 10:22:45 +05:30
|
|
|
big_info->payload_count_framing[0] = lll_adv_iso->payload_count;
|
|
|
|
big_info->payload_count_framing[1] = lll_adv_iso->payload_count >> 8;
|
|
|
|
big_info->payload_count_framing[2] = lll_adv_iso->payload_count >> 16;
|
|
|
|
big_info->payload_count_framing[3] = lll_adv_iso->payload_count >> 24;
|
|
|
|
big_info->payload_count_framing[4] = lll_adv_iso->payload_count >> 32;
|
2021-03-16 13:31:26 +05:30
|
|
|
big_info->payload_count_framing[4] &= ~BIT(7);
|
2021-01-15 17:08:16 +05:30
|
|
|
big_info->payload_count_framing[4] |= ((framing & 0x01) << 7);
|
2021-01-04 13:27:38 +05:30
|
|
|
|
2021-03-09 19:19:02 +05:30
|
|
|
/* Associate the ISO instance with an Extended Advertising instance */
|
2021-01-04 13:22:23 +05:30
|
|
|
lll_adv_iso->adv = &adv->lll;
|
|
|
|
|
2021-03-10 06:54:44 +05:30
|
|
|
/* Store the link buffer for ISO create and terminate complete event */
|
2021-03-10 06:57:56 +05:30
|
|
|
adv_iso->node_rx_complete.hdr.link = link_cmplt;
|
|
|
|
adv_iso->node_rx_terminate.hdr.link = link_term;
|
2021-01-19 16:04:51 +05:30
|
|
|
|
|
|
|
/* Initialise LLL header members */
|
2021-01-18 17:13:52 +05:30
|
|
|
lll_hdr_init(lll_adv_iso, adv_iso);
|
|
|
|
|
2022-02-16 11:55:21 +05:30
|
|
|
/* Start sending BIS empty data packet for each BIS */
|
2022-02-18 06:20:56 +05:30
|
|
|
ret = adv_iso_start(adv_iso, iso_interval_us);
|
2021-01-19 16:04:51 +05:30
|
|
|
if (ret) {
|
2022-06-06 09:28:28 +05:30
|
|
|
/* Failed to schedule BIG events */
|
|
|
|
|
|
|
|
/* Reset the association of ISO instance with the Extended
|
|
|
|
* Advertising Instance
|
|
|
|
*/
|
|
|
|
lll_adv_iso->adv = NULL;
|
|
|
|
|
|
|
|
/* Release allocated link buffers */
|
|
|
|
ll_rx_link_release(link_cmplt);
|
|
|
|
ll_rx_link_release(link_term);
|
|
|
|
|
2021-01-19 16:04:51 +05:30
|
|
|
return BT_HCI_ERR_CMD_DISALLOWED;
|
|
|
|
}
|
2020-11-26 14:03:27 +01:00
|
|
|
|
2021-03-09 19:19:02 +05:30
|
|
|
/* Associate the ISO instance with a Periodic Advertising */
|
|
|
|
lll_adv_sync->iso = lll_adv_iso;
|
|
|
|
|
|
|
|
/* Commit the BIGInfo in the ACAD field of Periodic Advertising */
|
|
|
|
lll_adv_sync_data_enqueue(lll_adv_sync, ter_idx);
|
|
|
|
|
2020-11-26 14:03:27 +01:00
|
|
|
return BT_HCI_ERR_SUCCESS;
|
2020-10-30 11:26:26 +01:00
|
|
|
}
|
|
|
|
|
2020-11-26 14:03:27 +01:00
|
|
|
uint8_t ll_big_test_create(uint8_t big_handle, uint8_t adv_handle,
|
|
|
|
uint8_t num_bis, uint32_t sdu_interval,
|
|
|
|
uint16_t iso_interval, uint8_t nse, uint16_t max_sdu,
|
|
|
|
uint16_t max_pdu, uint8_t phy, uint8_t packing,
|
|
|
|
uint8_t framing, uint8_t bn, uint8_t irc,
|
|
|
|
uint8_t pto, uint8_t encryption, uint8_t *bcode)
|
2020-10-30 11:26:26 +01:00
|
|
|
{
|
2020-11-26 14:03:27 +01:00
|
|
|
/* TODO: Implement */
|
|
|
|
ARG_UNUSED(big_handle);
|
|
|
|
ARG_UNUSED(adv_handle);
|
|
|
|
ARG_UNUSED(num_bis);
|
|
|
|
ARG_UNUSED(sdu_interval);
|
|
|
|
ARG_UNUSED(iso_interval);
|
|
|
|
ARG_UNUSED(nse);
|
|
|
|
ARG_UNUSED(max_sdu);
|
|
|
|
ARG_UNUSED(max_pdu);
|
|
|
|
ARG_UNUSED(phy);
|
|
|
|
ARG_UNUSED(packing);
|
|
|
|
ARG_UNUSED(framing);
|
|
|
|
ARG_UNUSED(bn);
|
|
|
|
ARG_UNUSED(irc);
|
|
|
|
ARG_UNUSED(pto);
|
|
|
|
ARG_UNUSED(encryption);
|
|
|
|
ARG_UNUSED(bcode);
|
|
|
|
|
|
|
|
return BT_HCI_ERR_CMD_DISALLOWED;
|
2020-10-30 11:26:26 +01:00
|
|
|
}
|
|
|
|
|
2020-12-01 15:38:13 +01:00
|
|
|
uint8_t ll_big_terminate(uint8_t big_handle, uint8_t reason)
|
2020-10-30 11:26:26 +01:00
|
|
|
{
|
2021-01-04 13:22:23 +05:30
|
|
|
struct lll_adv_sync *lll_adv_sync;
|
|
|
|
struct lll_adv_iso *lll_adv_iso;
|
2021-01-06 13:32:08 +05:30
|
|
|
struct ll_adv_iso_set *adv_iso;
|
2021-02-24 12:39:57 +05:30
|
|
|
struct pdu_adv *pdu_prev, *pdu;
|
2020-11-26 14:03:27 +01:00
|
|
|
struct node_rx_pdu *node_rx;
|
2021-01-04 13:22:23 +05:30
|
|
|
struct lll_adv *lll_adv;
|
2021-02-24 12:39:57 +05:30
|
|
|
struct ll_adv_set *adv;
|
|
|
|
uint8_t ter_idx;
|
2021-01-04 13:27:38 +05:30
|
|
|
uint8_t err;
|
2020-10-30 11:26:26 +01:00
|
|
|
|
2021-11-19 17:04:34 +05:30
|
|
|
adv_iso = adv_iso_get(big_handle);
|
2020-11-26 14:03:27 +01:00
|
|
|
if (!adv_iso) {
|
|
|
|
return BT_HCI_ERR_UNKNOWN_ADV_IDENTIFIER;
|
|
|
|
}
|
|
|
|
|
2021-01-04 13:22:23 +05:30
|
|
|
lll_adv_iso = &adv_iso->lll;
|
|
|
|
lll_adv = lll_adv_iso->adv;
|
|
|
|
if (!lll_adv) {
|
|
|
|
return BT_HCI_ERR_UNKNOWN_ADV_IDENTIFIER;
|
|
|
|
}
|
|
|
|
|
2021-03-16 13:31:26 +05:30
|
|
|
if (lll_adv_iso->term_req) {
|
|
|
|
return BT_HCI_ERR_CMD_DISALLOWED;
|
|
|
|
}
|
|
|
|
|
2021-01-04 13:22:23 +05:30
|
|
|
lll_adv_sync = lll_adv->sync;
|
2021-02-24 12:39:57 +05:30
|
|
|
adv = HDR_LLL2ULL(lll_adv);
|
|
|
|
|
|
|
|
/* Allocate next PDU */
|
2022-01-19 20:57:50 +05:30
|
|
|
err = ull_adv_sync_pdu_alloc(adv, ULL_ADV_PDU_EXTRA_DATA_ALLOC_IF_EXIST,
|
|
|
|
&pdu_prev, &pdu, NULL, NULL, &ter_idx);
|
2021-02-24 12:39:57 +05:30
|
|
|
if (err) {
|
|
|
|
return err;
|
|
|
|
}
|
2021-01-04 13:22:23 +05:30
|
|
|
|
2021-01-04 13:27:38 +05:30
|
|
|
/* Remove ACAD to AUX_SYNC_IND */
|
2021-02-24 12:39:57 +05:30
|
|
|
err = ull_adv_sync_pdu_set_clear(lll_adv_sync, pdu_prev, pdu,
|
|
|
|
0U, ULL_ADV_PDU_HDR_FIELD_ACAD, NULL);
|
2021-01-04 13:27:38 +05:30
|
|
|
if (err) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2021-02-24 12:39:57 +05:30
|
|
|
lll_adv_sync_data_enqueue(lll_adv_sync, ter_idx);
|
|
|
|
|
2021-03-16 13:31:26 +05:30
|
|
|
/* Prepare BIG terminate event, will be enqueued after tx flush */
|
2020-11-26 14:03:27 +01:00
|
|
|
node_rx = (void *)&adv_iso->node_rx_terminate;
|
|
|
|
node_rx->hdr.type = NODE_RX_TYPE_BIG_TERMINATE;
|
|
|
|
node_rx->hdr.handle = big_handle;
|
|
|
|
node_rx->hdr.rx_ftr.param = adv_iso;
|
|
|
|
|
2021-03-16 13:31:26 +05:30
|
|
|
if (reason == BT_HCI_ERR_REMOTE_USER_TERM_CONN) {
|
|
|
|
*((uint8_t *)node_rx->pdu) = BT_HCI_ERR_LOCALHOST_TERM_CONN;
|
|
|
|
} else {
|
|
|
|
*((uint8_t *)node_rx->pdu) = reason;
|
|
|
|
}
|
2021-03-10 06:57:56 +05:30
|
|
|
|
2021-03-16 13:31:26 +05:30
|
|
|
/* Request terminate procedure */
|
|
|
|
lll_adv_iso->term_reason = reason;
|
|
|
|
lll_adv_iso->term_req = 1U;
|
2021-03-10 06:57:56 +05:30
|
|
|
|
2020-11-26 14:03:27 +01:00
|
|
|
return BT_HCI_ERR_SUCCESS;
|
2020-10-30 11:26:26 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
int ull_adv_iso_init(void)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = init_reset();
|
|
|
|
if (err) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int ull_adv_iso_reset(void)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = init_reset();
|
|
|
|
if (err) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-01-19 20:57:50 +05:30
|
|
|
uint8_t ull_adv_iso_chm_update(void)
|
|
|
|
{
|
|
|
|
uint8_t handle;
|
|
|
|
|
|
|
|
handle = CONFIG_BT_CTLR_ADV_ISO_SET;
|
|
|
|
while (handle--) {
|
|
|
|
(void)adv_iso_chm_update(handle);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* TODO: Should failure due to Channel Map Update being already in
|
|
|
|
* progress be returned to caller?
|
|
|
|
*/
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ull_adv_iso_chm_complete(struct node_rx_hdr *rx)
|
|
|
|
{
|
|
|
|
struct lll_adv_sync *sync_lll;
|
|
|
|
struct lll_adv_iso *iso_lll;
|
|
|
|
struct lll_adv *adv_lll;
|
|
|
|
|
|
|
|
iso_lll = rx->rx_ftr.param;
|
|
|
|
adv_lll = iso_lll->adv;
|
|
|
|
sync_lll = adv_lll->sync;
|
|
|
|
|
|
|
|
/* Update Channel Map in BIGInfo in the Periodic Advertising PDU */
|
|
|
|
while (sync_lll->iso_chm_done_req != sync_lll->iso_chm_done_ack) {
|
|
|
|
sync_lll->iso_chm_done_ack = sync_lll->iso_chm_done_req;
|
|
|
|
|
|
|
|
adv_iso_chm_complete_commit(iso_lll);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-12-01 21:25:41 +01:00
|
|
|
#if defined(CONFIG_BT_CTLR_HCI_ADV_HANDLE_MAPPING)
|
2020-10-21 21:14:07 +02:00
|
|
|
uint8_t ll_adv_iso_by_hci_handle_get(uint8_t hci_handle, uint8_t *handle)
|
|
|
|
{
|
2021-01-06 13:32:08 +05:30
|
|
|
struct ll_adv_iso_set *adv_iso;
|
2020-10-21 21:14:07 +02:00
|
|
|
uint8_t idx;
|
|
|
|
|
|
|
|
adv_iso = &ll_adv_iso[0];
|
|
|
|
|
2021-11-23 21:34:04 +05:30
|
|
|
for (idx = 0U; idx < CONFIG_BT_CTLR_ADV_ISO_SET; idx++, adv_iso++) {
|
2021-02-22 13:36:43 +05:30
|
|
|
if (adv_iso->lll.adv &&
|
2020-10-21 21:14:07 +02:00
|
|
|
(adv_iso->hci_handle == hci_handle)) {
|
|
|
|
*handle = idx;
|
2021-11-16 13:04:21 +05:30
|
|
|
return 0U;
|
2020-10-21 21:14:07 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return BT_HCI_ERR_UNKNOWN_ADV_IDENTIFIER;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint8_t ll_adv_iso_by_hci_handle_new(uint8_t hci_handle, uint8_t *handle)
|
|
|
|
{
|
2021-01-06 13:32:08 +05:30
|
|
|
struct ll_adv_iso_set *adv_iso, *adv_iso_empty;
|
2020-10-21 21:14:07 +02:00
|
|
|
uint8_t idx;
|
|
|
|
|
|
|
|
adv_iso = &ll_adv_iso[0];
|
|
|
|
adv_iso_empty = NULL;
|
|
|
|
|
2021-11-23 21:34:04 +05:30
|
|
|
for (idx = 0U; idx < CONFIG_BT_CTLR_ADV_ISO_SET; idx++, adv_iso++) {
|
2021-02-22 13:36:43 +05:30
|
|
|
if (adv_iso->lll.adv) {
|
2020-10-21 21:14:07 +02:00
|
|
|
if (adv_iso->hci_handle == hci_handle) {
|
|
|
|
return BT_HCI_ERR_CMD_DISALLOWED;
|
|
|
|
}
|
|
|
|
} else if (!adv_iso_empty) {
|
|
|
|
adv_iso_empty = adv_iso;
|
|
|
|
*handle = idx;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (adv_iso_empty) {
|
2021-11-16 13:04:21 +05:30
|
|
|
memset(adv_iso_empty, 0U, sizeof(*adv_iso_empty));
|
2020-10-21 21:14:07 +02:00
|
|
|
adv_iso_empty->hci_handle = hci_handle;
|
2021-11-16 13:04:21 +05:30
|
|
|
return 0U;
|
2020-10-21 21:14:07 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return BT_HCI_ERR_MEM_CAPACITY_EXCEEDED;
|
|
|
|
}
|
2020-12-01 21:25:41 +01:00
|
|
|
#endif /* CONFIG_BT_CTLR_HCI_ADV_HANDLE_MAPPING */
|
2020-10-21 21:14:07 +02:00
|
|
|
|
2021-01-18 17:13:52 +05:30
|
|
|
void ull_adv_iso_offset_get(struct ll_adv_sync_set *sync)
|
|
|
|
{
|
|
|
|
static memq_link_t link;
|
2021-11-16 13:04:21 +05:30
|
|
|
static struct mayfly mfy = {0U, 0U, &link, NULL, mfy_iso_offset_get};
|
2021-01-18 17:13:52 +05:30
|
|
|
uint32_t ret;
|
|
|
|
|
|
|
|
mfy.param = sync;
|
|
|
|
ret = mayfly_enqueue(TICKER_USER_ID_ULL_HIGH, TICKER_USER_ID_ULL_LOW, 1,
|
|
|
|
&mfy);
|
|
|
|
LL_ASSERT(!ret);
|
|
|
|
}
|
|
|
|
|
2021-03-16 13:31:26 +05:30
|
|
|
void ull_adv_iso_done_complete(struct node_rx_event_done *done)
|
2021-01-19 16:04:51 +05:30
|
|
|
{
|
|
|
|
struct ll_adv_iso_set *adv_iso;
|
|
|
|
struct lll_adv_iso *lll;
|
|
|
|
struct node_rx_hdr *rx;
|
2021-03-10 06:54:44 +05:30
|
|
|
memq_link_t *link;
|
2021-01-19 16:04:51 +05:30
|
|
|
|
|
|
|
/* switch to normal prepare */
|
|
|
|
mfy_lll_prepare.fp = lll_adv_iso_prepare;
|
|
|
|
|
2021-02-18 13:02:24 +05:30
|
|
|
/* Get reference to ULL context */
|
|
|
|
adv_iso = CONTAINER_OF(done->param, struct ll_adv_iso_set, ull);
|
|
|
|
lll = &adv_iso->lll;
|
2021-01-19 16:04:51 +05:30
|
|
|
|
|
|
|
/* Prepare BIG complete event */
|
2021-03-10 06:54:44 +05:30
|
|
|
rx = (void *)&adv_iso->node_rx_complete;
|
|
|
|
link = rx->link;
|
2021-04-16 12:18:57 +05:30
|
|
|
if (!link) {
|
|
|
|
/* NOTE: When BIS events have overlapping prepare placed in
|
|
|
|
* in the pipeline, more than one done complete event
|
|
|
|
* will be generated, lets ignore the additional done
|
|
|
|
* events.
|
|
|
|
*/
|
|
|
|
return;
|
|
|
|
}
|
2021-03-10 06:54:44 +05:30
|
|
|
rx->link = NULL;
|
2021-03-16 13:31:26 +05:30
|
|
|
|
2021-01-19 16:04:51 +05:30
|
|
|
rx->type = NODE_RX_TYPE_BIG_COMPLETE;
|
|
|
|
rx->handle = lll->handle;
|
|
|
|
rx->rx_ftr.param = adv_iso;
|
|
|
|
|
2021-03-10 06:54:44 +05:30
|
|
|
ll_rx_put(link, rx);
|
2021-01-19 16:04:51 +05:30
|
|
|
ll_rx_sched();
|
|
|
|
}
|
|
|
|
|
2021-03-16 13:31:26 +05:30
|
|
|
void ull_adv_iso_done_terminate(struct node_rx_event_done *done)
|
|
|
|
{
|
|
|
|
struct ll_adv_iso_set *adv_iso;
|
|
|
|
struct lll_adv_iso *lll;
|
|
|
|
uint32_t ret;
|
|
|
|
|
|
|
|
/* Get reference to ULL context */
|
|
|
|
adv_iso = CONTAINER_OF(done->param, struct ll_adv_iso_set, ull);
|
|
|
|
lll = &adv_iso->lll;
|
|
|
|
|
2021-04-15 11:24:21 +05:30
|
|
|
/* Skip if terminated already (we come here if pipeline being flushed */
|
2021-11-16 13:08:26 +05:30
|
|
|
if (unlikely(lll->handle == LLL_ADV_HANDLE_INVALID)) {
|
2021-04-15 11:24:21 +05:30
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2021-03-16 13:31:26 +05:30
|
|
|
ret = ticker_stop(TICKER_INSTANCE_ID_CTLR, TICKER_USER_ID_ULL_HIGH,
|
|
|
|
(TICKER_ID_ADV_ISO_BASE + lll->handle),
|
2021-08-17 14:34:39 +05:30
|
|
|
ticker_stop_op_cb, adv_iso);
|
2021-03-16 13:31:26 +05:30
|
|
|
LL_ASSERT((ret == TICKER_STATUS_SUCCESS) ||
|
|
|
|
(ret == TICKER_STATUS_BUSY));
|
2021-04-15 11:24:21 +05:30
|
|
|
|
|
|
|
/* Invalidate the handle */
|
2021-11-16 13:08:26 +05:30
|
|
|
lll->handle = LLL_ADV_HANDLE_INVALID;
|
2021-03-16 13:31:26 +05:30
|
|
|
}
|
|
|
|
|
2021-11-23 21:34:04 +05:30
|
|
|
struct ll_adv_iso_set *ull_adv_iso_by_stream_get(uint16_t handle)
|
|
|
|
{
|
|
|
|
if (handle >= CONFIG_BT_CTLR_ADV_ISO_STREAM_COUNT) {
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return adv_iso_get(stream_pool[handle].big_handle);
|
|
|
|
}
|
|
|
|
|
2021-12-07 13:04:34 +05:30
|
|
|
struct lll_adv_iso_stream *ull_adv_iso_stream_get(uint16_t handle)
|
|
|
|
{
|
|
|
|
if (handle >= CONFIG_BT_CTLR_ADV_ISO_STREAM_COUNT) {
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return &stream_pool[handle];
|
|
|
|
}
|
|
|
|
|
|
|
|
struct lll_adv_iso_stream *ull_adv_iso_lll_stream_get(uint16_t handle)
|
|
|
|
{
|
|
|
|
return ull_adv_iso_stream_get(handle);
|
|
|
|
}
|
|
|
|
|
2021-11-23 21:34:04 +05:30
|
|
|
void ull_adv_iso_stream_release(struct ll_adv_iso_set *adv_iso)
|
|
|
|
{
|
|
|
|
struct lll_adv_iso *lll;
|
|
|
|
|
|
|
|
lll = &adv_iso->lll;
|
|
|
|
while (lll->num_bis--) {
|
|
|
|
struct lll_adv_iso_stream *stream;
|
2022-05-25 09:58:17 +05:30
|
|
|
uint16_t stream_handle;
|
2021-12-07 13:04:34 +05:30
|
|
|
memq_link_t *link;
|
2021-11-23 21:34:04 +05:30
|
|
|
|
2022-05-25 09:58:17 +05:30
|
|
|
stream_handle = lll->stream_handle[lll->num_bis];
|
|
|
|
stream = ull_adv_iso_stream_get(stream_handle);
|
2021-12-07 13:04:34 +05:30
|
|
|
|
|
|
|
LL_ASSERT(!stream->link_tx_free);
|
|
|
|
link = memq_deinit(&stream->memq_tx.head,
|
|
|
|
&stream->memq_tx.tail);
|
|
|
|
LL_ASSERT(link);
|
|
|
|
stream->link_tx_free = link;
|
|
|
|
|
2021-11-23 21:34:04 +05:30
|
|
|
mem_release(stream, &stream_free);
|
|
|
|
}
|
|
|
|
|
2022-05-25 09:52:18 +05:30
|
|
|
/* Remove Periodic Advertising association */
|
|
|
|
lll->adv->sync->iso = NULL;
|
|
|
|
|
|
|
|
/* Remove Extended Advertising association */
|
2021-11-23 21:34:04 +05:30
|
|
|
lll->adv = NULL;
|
|
|
|
}
|
|
|
|
|
2021-01-18 17:13:52 +05:30
|
|
|
static int init_reset(void)
|
|
|
|
{
|
2021-11-16 13:04:21 +05:30
|
|
|
/* Add initializations common to power up initialization and HCI reset
|
|
|
|
* initializations.
|
|
|
|
*/
|
2021-11-23 21:34:04 +05:30
|
|
|
|
|
|
|
mem_init((void *)stream_pool, sizeof(struct lll_adv_iso_stream),
|
|
|
|
CONFIG_BT_CTLR_ADV_ISO_STREAM_COUNT, &stream_free);
|
|
|
|
|
2021-01-18 17:13:52 +05:30
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-11-19 17:04:34 +05:30
|
|
|
static struct ll_adv_iso_set *adv_iso_get(uint8_t handle)
|
2021-01-18 17:13:52 +05:30
|
|
|
{
|
|
|
|
if (handle >= CONFIG_BT_CTLR_ADV_SET) {
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return &ll_adv_iso[handle];
|
|
|
|
}
|
|
|
|
|
2021-11-23 21:34:04 +05:30
|
|
|
static struct stream *adv_iso_stream_acquire(void)
|
|
|
|
{
|
|
|
|
return mem_acquire(&stream_free);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint16_t adv_iso_stream_handle_get(struct lll_adv_iso_stream *stream)
|
|
|
|
{
|
|
|
|
return mem_index_get(stream, stream_pool, sizeof(*stream));
|
|
|
|
}
|
|
|
|
|
2021-11-19 17:02:13 +05:30
|
|
|
static uint8_t ptc_calc(const struct lll_adv_iso *lll, uint32_t latency_pdu,
|
|
|
|
uint32_t latency_packing, uint32_t ctrl_spacing)
|
|
|
|
{
|
|
|
|
uint32_t reserve;
|
|
|
|
|
|
|
|
reserve = latency_packing + ctrl_spacing +
|
|
|
|
EVENT_OVERHEAD_START_US + EVENT_OVERHEAD_END_US;
|
|
|
|
if (reserve < latency_pdu) {
|
2022-09-10 12:32:58 +05:30
|
|
|
uint8_t ptc;
|
|
|
|
|
|
|
|
/* Possible maximum Pre-transmission Subevents per BIS */
|
|
|
|
ptc = ((latency_pdu - reserve) / (lll->sub_interval * lll->bn *
|
|
|
|
lll->num_bis)) *
|
|
|
|
lll->bn;
|
|
|
|
|
|
|
|
/* Retrict to a maximum Pre-Transmission Subevents per BIS */
|
|
|
|
ptc = MIN(ptc, 1U);
|
|
|
|
|
|
|
|
return ptc;
|
2021-11-19 17:02:13 +05:30
|
|
|
}
|
|
|
|
|
|
|
|
return 0U;
|
|
|
|
}
|
|
|
|
|
2021-11-23 21:34:04 +05:30
|
|
|
static uint32_t adv_iso_start(struct ll_adv_iso_set *adv_iso,
|
2022-02-18 06:20:56 +05:30
|
|
|
uint32_t iso_interval_us)
|
2020-10-30 11:26:26 +01:00
|
|
|
{
|
|
|
|
uint32_t ticks_slot_overhead;
|
2022-04-22 17:48:07 +05:30
|
|
|
struct lll_adv_iso *lll_iso;
|
2021-05-18 10:41:03 +05:30
|
|
|
uint32_t ticks_slot_offset;
|
2020-10-30 11:26:26 +01:00
|
|
|
uint32_t volatile ret_cb;
|
2022-02-18 06:20:56 +05:30
|
|
|
uint32_t ticks_anchor;
|
2022-04-22 17:48:07 +05:30
|
|
|
uint32_t ctrl_spacing;
|
|
|
|
uint32_t pdu_spacing;
|
2022-02-18 06:20:56 +05:30
|
|
|
uint32_t ticks_slot;
|
2020-10-30 11:26:26 +01:00
|
|
|
uint32_t slot_us;
|
|
|
|
uint32_t ret;
|
2022-02-18 06:20:56 +05:30
|
|
|
int err;
|
2020-10-30 11:26:26 +01:00
|
|
|
|
|
|
|
ull_hdr_init(&adv_iso->ull);
|
|
|
|
|
2022-04-22 17:48:07 +05:30
|
|
|
lll_iso = &adv_iso->lll;
|
|
|
|
|
|
|
|
pdu_spacing = PDU_BIS_US(lll_iso->max_pdu, lll_iso->enc, lll_iso->phy,
|
|
|
|
lll_iso->phy_flags) +
|
|
|
|
EVENT_MSS_US;
|
|
|
|
ctrl_spacing = PDU_BIS_US(sizeof(struct pdu_big_ctrl), lll_iso->enc,
|
|
|
|
lll_iso->phy, lll_iso->phy_flags) +
|
|
|
|
EVENT_IFS_US;
|
|
|
|
slot_us = (pdu_spacing * lll_iso->nse * lll_iso->num_bis) +
|
|
|
|
ctrl_spacing;
|
|
|
|
slot_us += EVENT_OVERHEAD_START_US + EVENT_OVERHEAD_END_US;
|
2020-10-30 11:26:26 +01:00
|
|
|
|
2021-11-16 13:04:21 +05:30
|
|
|
adv_iso->ull.ticks_active_to_start = 0U;
|
2021-04-05 12:56:51 +05:30
|
|
|
adv_iso->ull.ticks_prepare_to_start =
|
2020-10-30 11:26:26 +01:00
|
|
|
HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
|
2021-04-05 12:56:51 +05:30
|
|
|
adv_iso->ull.ticks_preempt_to_start =
|
2020-10-30 11:26:26 +01:00
|
|
|
HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
|
2021-04-05 12:56:51 +05:30
|
|
|
adv_iso->ull.ticks_slot = HAL_TICKER_US_TO_TICKS(slot_us);
|
2020-10-30 11:26:26 +01:00
|
|
|
|
2021-05-18 10:41:03 +05:30
|
|
|
ticks_slot_offset = MAX(adv_iso->ull.ticks_active_to_start,
|
|
|
|
adv_iso->ull.ticks_prepare_to_start);
|
2020-10-30 11:26:26 +01:00
|
|
|
if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
|
2021-05-18 10:41:03 +05:30
|
|
|
ticks_slot_overhead = ticks_slot_offset;
|
2020-10-30 11:26:26 +01:00
|
|
|
} else {
|
2021-11-16 13:04:21 +05:30
|
|
|
ticks_slot_overhead = 0U;
|
2020-10-30 11:26:26 +01:00
|
|
|
}
|
2022-02-18 06:20:56 +05:30
|
|
|
ticks_slot = adv_iso->ull.ticks_slot + ticks_slot_overhead;
|
|
|
|
|
|
|
|
/* Find the slot after Periodic Advertisings events */
|
2022-05-13 16:44:49 +05:30
|
|
|
err = ull_sched_adv_aux_sync_free_slot_get(TICKER_USER_ID_THREAD,
|
|
|
|
ticks_slot, &ticks_anchor);
|
2022-08-31 09:56:49 +05:30
|
|
|
if (!err) {
|
|
|
|
ticks_anchor += HAL_TICKER_US_TO_TICKS(
|
2022-09-18 06:58:52 +05:30
|
|
|
MAX(EVENT_MAFS_US,
|
|
|
|
EVENT_OVERHEAD_START_US) +
|
|
|
|
(EVENT_TICKER_RES_MARGIN_US << 1));
|
2022-08-31 09:56:49 +05:30
|
|
|
} else {
|
2022-09-09 11:11:46 +02:00
|
|
|
ticks_anchor = ticker_ticks_now_get() +
|
|
|
|
HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_START_US);
|
2022-02-18 06:20:56 +05:30
|
|
|
}
|
2020-10-30 11:26:26 +01:00
|
|
|
|
2021-01-19 16:04:51 +05:30
|
|
|
/* setup to use ISO create prepare function for first radio event */
|
|
|
|
mfy_lll_prepare.fp = lll_adv_iso_create_prepare;
|
|
|
|
|
2020-10-30 11:26:26 +01:00
|
|
|
ret_cb = TICKER_STATUS_BUSY;
|
2021-02-18 13:25:50 +05:30
|
|
|
ret = ticker_start(TICKER_INSTANCE_ID_CTLR, TICKER_USER_ID_THREAD,
|
2022-04-22 17:48:07 +05:30
|
|
|
(TICKER_ID_ADV_ISO_BASE + lll_iso->handle),
|
2022-02-16 11:55:21 +05:30
|
|
|
ticks_anchor, 0U,
|
2020-10-30 11:26:26 +01:00
|
|
|
HAL_TICKER_US_TO_TICKS(iso_interval_us),
|
|
|
|
HAL_TICKER_REMAINDER(iso_interval_us),
|
2022-02-18 06:20:56 +05:30
|
|
|
TICKER_NULL_LAZY, ticks_slot, ticker_cb, adv_iso,
|
2020-10-30 11:26:26 +01:00
|
|
|
ull_ticker_status_give, (void *)&ret_cb);
|
|
|
|
ret = ull_ticker_status_take(ret, &ret_cb);
|
|
|
|
|
2021-01-19 16:04:51 +05:30
|
|
|
return ret;
|
2020-10-30 11:26:26 +01:00
|
|
|
}
|
|
|
|
|
2022-01-19 20:57:50 +05:30
|
|
|
static uint8_t adv_iso_chm_update(uint8_t big_handle)
|
|
|
|
{
|
|
|
|
struct ll_adv_iso_set *adv_iso;
|
|
|
|
struct lll_adv_iso *lll_iso;
|
|
|
|
|
|
|
|
adv_iso = adv_iso_get(big_handle);
|
|
|
|
if (!adv_iso) {
|
|
|
|
return BT_HCI_ERR_UNKNOWN_ADV_IDENTIFIER;
|
|
|
|
}
|
|
|
|
|
|
|
|
lll_iso = &adv_iso->lll;
|
|
|
|
if (lll_iso->term_req ||
|
|
|
|
(lll_iso->chm_req != lll_iso->chm_ack)) {
|
|
|
|
return BT_HCI_ERR_CMD_DISALLOWED;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Request channel map update procedure */
|
|
|
|
lll_iso->chm_chan_count = ull_chan_map_get(lll_iso->chm_chan_map);
|
|
|
|
lll_iso->chm_req++;
|
|
|
|
|
|
|
|
return BT_HCI_ERR_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void adv_iso_chm_complete_commit(struct lll_adv_iso *lll_iso)
|
|
|
|
{
|
|
|
|
uint8_t hdr_data[ULL_ADV_HDR_DATA_LEN_SIZE +
|
|
|
|
ULL_ADV_HDR_DATA_ACAD_PTR_SIZE];
|
|
|
|
struct pdu_adv *pdu_prev, *pdu;
|
|
|
|
struct lll_adv_sync *lll_sync;
|
|
|
|
struct pdu_big_info *bi;
|
|
|
|
struct ll_adv_set *adv;
|
|
|
|
uint8_t acad_len;
|
|
|
|
uint8_t ter_idx;
|
|
|
|
uint8_t ad_len;
|
|
|
|
uint8_t *acad;
|
|
|
|
uint8_t *ad;
|
|
|
|
uint8_t len;
|
|
|
|
uint8_t err;
|
|
|
|
|
|
|
|
/* Allocate next PDU */
|
|
|
|
adv = HDR_LLL2ULL(lll_iso->adv);
|
|
|
|
err = ull_adv_sync_pdu_alloc(adv, ULL_ADV_PDU_EXTRA_DATA_ALLOC_IF_EXIST,
|
|
|
|
&pdu_prev, &pdu, NULL, NULL, &ter_idx);
|
|
|
|
LL_ASSERT(!err);
|
|
|
|
|
|
|
|
/* Get the size of current ACAD, first octet returns the old length and
|
|
|
|
* followed by pointer to previous offset to ACAD in the PDU.
|
|
|
|
*/
|
|
|
|
lll_sync = adv->lll.sync;
|
|
|
|
hdr_data[ULL_ADV_HDR_DATA_LEN_OFFSET] = 0U;
|
|
|
|
err = ull_adv_sync_pdu_set_clear(lll_sync, pdu_prev, pdu,
|
|
|
|
ULL_ADV_PDU_HDR_FIELD_ACAD, 0U,
|
|
|
|
&hdr_data);
|
|
|
|
LL_ASSERT(!err);
|
|
|
|
|
|
|
|
/* Dev assert if ACAD empty */
|
|
|
|
LL_ASSERT(hdr_data[ULL_ADV_HDR_DATA_LEN_OFFSET]);
|
|
|
|
|
|
|
|
/* Get the pointer, prev content and size of current ACAD */
|
|
|
|
err = ull_adv_sync_pdu_set_clear(lll_sync, pdu_prev, pdu,
|
|
|
|
ULL_ADV_PDU_HDR_FIELD_ACAD, 0U,
|
|
|
|
&hdr_data);
|
|
|
|
LL_ASSERT(!err);
|
|
|
|
|
|
|
|
/* Find the BIGInfo */
|
|
|
|
acad_len = hdr_data[ULL_ADV_HDR_DATA_LEN_OFFSET];
|
|
|
|
len = acad_len;
|
|
|
|
(void)memcpy(&acad, &hdr_data[ULL_ADV_HDR_DATA_ACAD_PTR_OFFSET],
|
|
|
|
sizeof(acad));
|
|
|
|
ad = acad;
|
|
|
|
do {
|
|
|
|
ad_len = ad[PDU_ADV_DATA_HEADER_LEN_OFFSET];
|
|
|
|
if (ad_len &&
|
|
|
|
(ad[PDU_ADV_DATA_HEADER_TYPE_OFFSET] == BT_DATA_BIG_INFO)) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
ad_len += 1U;
|
|
|
|
|
|
|
|
LL_ASSERT(ad_len <= len);
|
|
|
|
|
|
|
|
ad += ad_len;
|
|
|
|
len -= ad_len;
|
|
|
|
} while (len);
|
|
|
|
LL_ASSERT(len);
|
|
|
|
|
|
|
|
/* Get reference to BIGInfo */
|
|
|
|
bi = (void *)&ad[PDU_ADV_DATA_HEADER_DATA_OFFSET];
|
|
|
|
|
|
|
|
/* Copy the new/current Channel Map */
|
|
|
|
pdu_big_info_chan_map_phy_set(bi->chm_phy, lll_iso->data_chan_map,
|
|
|
|
lll_iso->phy);
|
|
|
|
|
|
|
|
/* Commit the new PDU Buffer */
|
|
|
|
lll_adv_sync_data_enqueue(lll_sync, ter_idx);
|
|
|
|
}
|
|
|
|
|
2021-01-18 17:13:52 +05:30
|
|
|
static void mfy_iso_offset_get(void *param)
|
2020-10-21 21:14:07 +02:00
|
|
|
{
|
2022-01-19 20:57:50 +05:30
|
|
|
struct lll_adv_sync *lll_sync;
|
2021-01-18 17:13:52 +05:30
|
|
|
struct ll_adv_sync_set *sync;
|
|
|
|
struct lll_adv_iso *lll_iso;
|
|
|
|
uint32_t ticks_to_expire;
|
|
|
|
struct pdu_big_info *bi;
|
|
|
|
uint32_t ticks_current;
|
2021-03-15 16:13:22 +05:30
|
|
|
uint64_t payload_count;
|
2021-01-18 17:13:52 +05:30
|
|
|
struct pdu_adv *pdu;
|
|
|
|
uint8_t ticker_id;
|
2021-03-15 16:13:22 +05:30
|
|
|
uint16_t lazy;
|
2021-01-18 17:13:52 +05:30
|
|
|
uint8_t retry;
|
|
|
|
uint8_t id;
|
|
|
|
|
|
|
|
sync = param;
|
2022-01-19 20:57:50 +05:30
|
|
|
lll_sync = &sync->lll;
|
|
|
|
lll_iso = lll_sync->iso;
|
2021-01-18 17:13:52 +05:30
|
|
|
ticker_id = TICKER_ID_ADV_ISO_BASE + lll_iso->handle;
|
|
|
|
|
|
|
|
id = TICKER_NULL;
|
|
|
|
ticks_to_expire = 0U;
|
|
|
|
ticks_current = 0U;
|
|
|
|
retry = 4U;
|
|
|
|
do {
|
|
|
|
uint32_t volatile ret_cb;
|
|
|
|
uint32_t ticks_previous;
|
|
|
|
uint32_t ret;
|
2021-05-19 07:03:27 +05:30
|
|
|
bool success;
|
2021-01-18 17:13:52 +05:30
|
|
|
|
|
|
|
ticks_previous = ticks_current;
|
|
|
|
|
|
|
|
ret_cb = TICKER_STATUS_BUSY;
|
2021-03-15 16:13:22 +05:30
|
|
|
ret = ticker_next_slot_get_ext(TICKER_INSTANCE_ID_CTLR,
|
|
|
|
TICKER_USER_ID_ULL_LOW,
|
|
|
|
&id, &ticks_current,
|
2021-03-15 16:08:23 +05:30
|
|
|
&ticks_to_expire, NULL, &lazy,
|
2021-03-15 16:13:22 +05:30
|
|
|
NULL, NULL,
|
|
|
|
ticker_op_cb, (void *)&ret_cb);
|
2021-01-18 17:13:52 +05:30
|
|
|
if (ret == TICKER_STATUS_BUSY) {
|
2021-11-16 13:04:21 +05:30
|
|
|
/* Busy wait until Ticker Job is enabled after any Radio
|
|
|
|
* event is done using the Radio hardware. Ticker Job
|
|
|
|
* ISR is disabled during Radio events in LOW_LAT
|
|
|
|
* feature to avoid Radio ISR latencies.
|
|
|
|
*/
|
2021-01-18 17:13:52 +05:30
|
|
|
while (ret_cb == TICKER_STATUS_BUSY) {
|
|
|
|
ticker_job_sched(TICKER_INSTANCE_ID_CTLR,
|
|
|
|
TICKER_USER_ID_ULL_LOW);
|
|
|
|
}
|
|
|
|
}
|
2020-10-21 21:14:07 +02:00
|
|
|
|
2021-05-19 07:03:27 +05:30
|
|
|
success = (ret_cb == TICKER_STATUS_SUCCESS);
|
|
|
|
LL_ASSERT(success);
|
2021-01-18 17:13:52 +05:30
|
|
|
|
|
|
|
LL_ASSERT((ticks_current == ticks_previous) || retry--);
|
|
|
|
|
|
|
|
LL_ASSERT(id != TICKER_NULL);
|
|
|
|
} while (id != ticker_id);
|
|
|
|
|
2021-03-15 16:13:22 +05:30
|
|
|
payload_count = lll_iso->payload_count + ((lll_iso->latency_prepare +
|
|
|
|
lazy) * lll_iso->bn);
|
|
|
|
|
2022-01-19 20:57:50 +05:30
|
|
|
pdu = lll_adv_sync_data_latest_peek(lll_sync);
|
2021-01-18 17:13:52 +05:30
|
|
|
bi = big_info_get(pdu);
|
2021-11-16 13:04:21 +05:30
|
|
|
big_info_offset_fill(bi, ticks_to_expire, 0U);
|
2021-03-15 16:13:22 +05:30
|
|
|
bi->payload_count_framing[0] = payload_count;
|
|
|
|
bi->payload_count_framing[1] = payload_count >> 8;
|
|
|
|
bi->payload_count_framing[2] = payload_count >> 16;
|
|
|
|
bi->payload_count_framing[3] = payload_count >> 24;
|
|
|
|
bi->payload_count_framing[4] = payload_count >> 32;
|
|
|
|
bi->payload_count_framing[4] &= ~0x7F;
|
|
|
|
bi->payload_count_framing[4] |= (payload_count >> 32) & 0x7F;
|
2022-01-19 20:57:50 +05:30
|
|
|
|
|
|
|
/* Update Channel Map in the BIGInfo until Thread context gets a
|
|
|
|
* chance to update the PDU with new Channel Map.
|
|
|
|
*/
|
|
|
|
if (lll_sync->iso_chm_done_req != lll_sync->iso_chm_done_ack) {
|
|
|
|
pdu_big_info_chan_map_phy_set(bi->chm_phy,
|
|
|
|
lll_iso->data_chan_map,
|
|
|
|
lll_iso->phy);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pdu_big_info_chan_map_phy_set(uint8_t *chm_phy, uint8_t *chan_map,
|
|
|
|
uint8_t phy)
|
|
|
|
{
|
|
|
|
(void)memcpy(chm_phy, chan_map, PDU_CHANNEL_MAP_SIZE);
|
|
|
|
chm_phy[4] &= 0x1F;
|
|
|
|
chm_phy[4] |= ((find_lsb_set(phy) - 1U) << 5);
|
2020-10-21 21:14:07 +02:00
|
|
|
}
|
2020-10-02 14:29:47 +02:00
|
|
|
|
2021-01-18 17:13:52 +05:30
|
|
|
static inline struct pdu_big_info *big_info_get(struct pdu_adv *pdu)
|
2020-10-02 14:29:47 +02:00
|
|
|
{
|
2021-01-18 17:13:52 +05:30
|
|
|
struct pdu_adv_com_ext_adv *p;
|
|
|
|
struct pdu_adv_ext_hdr *h;
|
|
|
|
uint8_t *ptr;
|
2020-10-21 21:14:07 +02:00
|
|
|
|
2021-01-18 17:13:52 +05:30
|
|
|
p = (void *)&pdu->adv_ext_ind;
|
|
|
|
h = (void *)p->ext_hdr_adv_data;
|
|
|
|
ptr = h->data;
|
|
|
|
|
2021-09-03 07:07:08 +05:30
|
|
|
/* No AdvA and TargetA */
|
2021-01-18 17:13:52 +05:30
|
|
|
|
2021-09-03 07:07:08 +05:30
|
|
|
/* traverse through CTE Info, if present */
|
|
|
|
if (h->cte_info) {
|
|
|
|
ptr += sizeof(struct pdu_cte_info);
|
|
|
|
}
|
|
|
|
|
2021-09-03 07:07:08 +05:30
|
|
|
/* traverse through ADI, if present */
|
|
|
|
if (h->adi) {
|
|
|
|
ptr += sizeof(struct pdu_adv_adi);
|
|
|
|
}
|
|
|
|
|
2021-09-03 07:07:08 +05:30
|
|
|
/* traverse through aux ptr, if present */
|
2021-01-18 17:13:52 +05:30
|
|
|
if (h->aux_ptr) {
|
|
|
|
ptr += sizeof(struct pdu_adv_aux_ptr);
|
|
|
|
}
|
|
|
|
|
2021-09-03 07:07:08 +05:30
|
|
|
/* No SyncInfo */
|
|
|
|
|
|
|
|
/* traverse through Tx Power, if present */
|
2021-01-18 17:13:52 +05:30
|
|
|
if (h->tx_pwr) {
|
|
|
|
ptr++;
|
|
|
|
}
|
|
|
|
|
2021-09-03 07:07:08 +05:30
|
|
|
/* FIXME: Parse and find the Length encoded AD Format */
|
2021-01-18 17:13:52 +05:30
|
|
|
ptr += 2;
|
|
|
|
|
|
|
|
return (void *)ptr;
|
2020-11-26 14:03:27 +01:00
|
|
|
}
|
2020-10-30 11:26:26 +01:00
|
|
|
|
2021-01-18 17:13:52 +05:30
|
|
|
static inline void big_info_offset_fill(struct pdu_big_info *bi,
|
|
|
|
uint32_t ticks_offset,
|
|
|
|
uint32_t start_us)
|
|
|
|
{
|
|
|
|
uint32_t offs;
|
|
|
|
|
|
|
|
offs = HAL_TICKER_TICKS_TO_US(ticks_offset) - start_us;
|
|
|
|
offs = offs / OFFS_UNIT_30_US;
|
2021-11-16 13:04:21 +05:30
|
|
|
if (!!(offs >> OFFS_UNIT_BITS)) {
|
2021-11-16 13:00:47 +05:30
|
|
|
bi->offs = sys_cpu_to_le16(offs / (OFFS_UNIT_300_US /
|
|
|
|
OFFS_UNIT_30_US));
|
2021-01-18 17:13:52 +05:30
|
|
|
bi->offs_units = 1U;
|
|
|
|
} else {
|
2021-11-16 13:00:47 +05:30
|
|
|
bi->offs = sys_cpu_to_le16(offs);
|
2021-01-18 17:13:52 +05:30
|
|
|
bi->offs_units = 0U;
|
|
|
|
}
|
|
|
|
}
|
2020-10-30 11:26:26 +01:00
|
|
|
|
2021-09-15 11:48:21 +05:30
|
|
|
static void ticker_cb(uint32_t ticks_at_expire, uint32_t ticks_drift,
|
|
|
|
uint32_t remainder, uint16_t lazy, uint8_t force,
|
|
|
|
void *param)
|
2020-11-26 14:03:27 +01:00
|
|
|
{
|
|
|
|
static struct lll_prepare_param p;
|
2021-01-06 13:32:08 +05:30
|
|
|
struct ll_adv_iso_set *adv_iso = param;
|
2020-11-26 14:03:27 +01:00
|
|
|
uint32_t ret;
|
|
|
|
uint8_t ref;
|
2020-10-30 11:26:26 +01:00
|
|
|
|
2020-11-26 14:03:27 +01:00
|
|
|
DEBUG_RADIO_PREPARE_A(1);
|
2020-10-21 21:14:07 +02:00
|
|
|
|
2020-11-26 14:03:27 +01:00
|
|
|
/* Increment prepare reference count */
|
|
|
|
ref = ull_ref_inc(&adv_iso->ull);
|
|
|
|
LL_ASSERT(ref);
|
2020-10-21 21:14:07 +02:00
|
|
|
|
2020-11-26 14:03:27 +01:00
|
|
|
/* Append timing parameters */
|
|
|
|
p.ticks_at_expire = ticks_at_expire;
|
|
|
|
p.remainder = remainder;
|
|
|
|
p.lazy = lazy;
|
2021-03-03 15:41:55 +01:00
|
|
|
p.force = force;
|
2021-01-06 13:32:08 +05:30
|
|
|
p.param = &adv_iso->lll;
|
2021-01-19 16:04:51 +05:30
|
|
|
mfy_lll_prepare.param = &p;
|
2020-10-02 14:29:47 +02:00
|
|
|
|
2020-11-26 14:03:27 +01:00
|
|
|
/* Kick LLL prepare */
|
2021-01-19 16:04:51 +05:30
|
|
|
ret = mayfly_enqueue(TICKER_USER_ID_ULL_HIGH, TICKER_USER_ID_LLL, 0,
|
|
|
|
&mfy_lll_prepare);
|
2020-11-26 14:03:27 +01:00
|
|
|
LL_ASSERT(!ret);
|
2020-10-02 14:29:47 +02:00
|
|
|
|
2020-11-26 14:03:27 +01:00
|
|
|
DEBUG_RADIO_PREPARE_A(1);
|
2021-01-18 17:13:52 +05:30
|
|
|
}
|
|
|
|
|
|
|
|
static void ticker_op_cb(uint32_t status, void *param)
|
|
|
|
{
|
|
|
|
*((uint32_t volatile *)param) = status;
|
2020-10-02 14:29:47 +02:00
|
|
|
}
|
|
|
|
|
2021-08-17 14:34:39 +05:30
|
|
|
static void ticker_stop_op_cb(uint32_t status, void *param)
|
2021-04-15 11:24:21 +05:30
|
|
|
{
|
|
|
|
static memq_link_t link;
|
2021-11-16 13:04:21 +05:30
|
|
|
static struct mayfly mfy = {0U, 0U, &link, NULL, adv_iso_disable};
|
2021-08-16 16:50:07 +05:30
|
|
|
uint32_t ret;
|
|
|
|
|
|
|
|
LL_ASSERT(status == TICKER_STATUS_SUCCESS);
|
|
|
|
|
|
|
|
/* Check if any pending LLL events that need to be aborted */
|
|
|
|
mfy.param = param;
|
|
|
|
ret = mayfly_enqueue(TICKER_USER_ID_ULL_LOW,
|
2021-11-16 13:04:21 +05:30
|
|
|
TICKER_USER_ID_ULL_HIGH, 0U, &mfy);
|
2021-08-16 16:50:07 +05:30
|
|
|
LL_ASSERT(!ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void adv_iso_disable(void *param)
|
|
|
|
{
|
2021-04-15 11:24:21 +05:30
|
|
|
struct ll_adv_iso_set *adv_iso;
|
|
|
|
struct ull_hdr *hdr;
|
|
|
|
|
2021-08-16 16:50:07 +05:30
|
|
|
/* Check ref count to determine if any pending LLL events in pipeline */
|
2021-04-15 11:24:21 +05:30
|
|
|
adv_iso = param;
|
|
|
|
hdr = &adv_iso->ull;
|
|
|
|
if (ull_ref_get(hdr)) {
|
2021-08-16 16:50:07 +05:30
|
|
|
static memq_link_t link;
|
2021-11-16 13:04:21 +05:30
|
|
|
static struct mayfly mfy = {0U, 0U, &link, NULL, lll_disable};
|
2021-04-15 11:24:21 +05:30
|
|
|
uint32_t ret;
|
|
|
|
|
2021-08-16 16:50:07 +05:30
|
|
|
mfy.param = &adv_iso->lll;
|
|
|
|
|
|
|
|
/* Setup disabled callback to be called when ref count
|
|
|
|
* returns to zero.
|
|
|
|
*/
|
2021-04-15 11:24:21 +05:30
|
|
|
LL_ASSERT(!hdr->disabled_cb);
|
|
|
|
hdr->disabled_param = mfy.param;
|
|
|
|
hdr->disabled_cb = disabled_cb;
|
|
|
|
|
2021-08-16 16:50:07 +05:30
|
|
|
/* Trigger LLL disable */
|
|
|
|
ret = mayfly_enqueue(TICKER_USER_ID_ULL_HIGH,
|
2021-11-16 13:04:21 +05:30
|
|
|
TICKER_USER_ID_LLL, 0U, &mfy);
|
2021-04-15 11:24:21 +05:30
|
|
|
LL_ASSERT(!ret);
|
|
|
|
} else {
|
2021-08-16 16:50:07 +05:30
|
|
|
/* No pending LLL events */
|
|
|
|
disabled_cb(&adv_iso->lll);
|
2021-04-15 11:24:21 +05:30
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void disabled_cb(void *param)
|
|
|
|
{
|
|
|
|
static memq_link_t link;
|
2021-11-16 13:04:21 +05:30
|
|
|
static struct mayfly mfy = {0U, 0U, &link, NULL, tx_lll_flush};
|
2021-04-15 11:24:21 +05:30
|
|
|
uint32_t ret;
|
|
|
|
|
|
|
|
mfy.param = param;
|
|
|
|
ret = mayfly_enqueue(TICKER_USER_ID_ULL_HIGH,
|
2021-11-16 13:04:21 +05:30
|
|
|
TICKER_USER_ID_LLL, 0U, &mfy);
|
2021-04-15 11:24:21 +05:30
|
|
|
LL_ASSERT(!ret);
|
|
|
|
}
|
|
|
|
|
2020-11-04 17:22:33 +01:00
|
|
|
static void tx_lll_flush(void *param)
|
|
|
|
{
|
2021-04-15 11:24:21 +05:30
|
|
|
struct ll_adv_iso_set *adv_iso;
|
|
|
|
struct lll_adv_iso *lll;
|
2021-03-10 06:57:56 +05:30
|
|
|
struct node_rx_pdu *rx;
|
|
|
|
memq_link_t *link;
|
2022-05-25 09:58:17 +05:30
|
|
|
uint8_t num_bis;
|
2021-03-10 06:57:56 +05:30
|
|
|
|
2021-04-15 11:24:21 +05:30
|
|
|
/* Get reference to ULL context */
|
|
|
|
lll = param;
|
|
|
|
|
2022-05-25 09:58:17 +05:30
|
|
|
/* Flush TX */
|
|
|
|
num_bis = lll->num_bis;
|
|
|
|
while (num_bis--) {
|
|
|
|
struct lll_adv_iso_stream *stream;
|
|
|
|
struct node_tx_iso *tx;
|
|
|
|
uint16_t stream_handle;
|
|
|
|
memq_link_t *link;
|
|
|
|
uint16_t handle;
|
|
|
|
|
|
|
|
stream_handle = lll->stream_handle[num_bis];
|
2022-09-17 06:25:26 +05:30
|
|
|
handle = LL_BIS_ADV_HANDLE_FROM_IDX(stream_handle);
|
2022-05-25 09:58:17 +05:30
|
|
|
stream = ull_adv_iso_stream_get(stream_handle);
|
|
|
|
|
|
|
|
link = memq_dequeue(stream->memq_tx.tail, &stream->memq_tx.head,
|
|
|
|
(void **)&tx);
|
|
|
|
while (link) {
|
|
|
|
tx->next = link;
|
|
|
|
ull_iso_lll_ack_enqueue(handle, tx);
|
|
|
|
|
|
|
|
link = memq_dequeue(stream->memq_tx.tail,
|
|
|
|
&stream->memq_tx.head,
|
|
|
|
(void **)&tx);
|
|
|
|
}
|
|
|
|
}
|
2021-03-10 06:57:56 +05:30
|
|
|
|
|
|
|
/* Get the terminate structure reserved in the ISO context.
|
|
|
|
* The terminate reason and connection handle should already be
|
|
|
|
* populated before this mayfly function was scheduled.
|
|
|
|
*/
|
2022-05-25 09:58:17 +05:30
|
|
|
adv_iso = HDR_LLL2ULL(lll);
|
2021-03-10 06:57:56 +05:30
|
|
|
rx = (void *)&adv_iso->node_rx_terminate;
|
|
|
|
link = rx->hdr.link;
|
|
|
|
LL_ASSERT(link);
|
|
|
|
rx->hdr.link = NULL;
|
|
|
|
|
|
|
|
/* Enqueue the terminate towards ULL context */
|
|
|
|
ull_rx_put(link, rx);
|
|
|
|
ull_rx_sched();
|
2020-11-04 17:22:33 +01:00
|
|
|
}
|