zephyr/arch/arm/soc/fsl_frdm_k64f/Kconfig

# Kconfig - FSL FRDM K64F platform configuration options

#
# Copyright (c) 2014-2016 Wind River Systems, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#

if SOC_FSL_FRDM_K64F
config SOC
	default fsl_frdm_k64f

config SRAM_BASE_ADDRESS
	default 0x20000000

config FLASH_BASE_ADDRESS
	default 0x00000000

config NUM_IRQ_PRIO_BITS
	int
	default 4

config NUM_IRQS
	int
	# must be >= the highest interrupt number used
	default 86

config SYS_CLOCK_HW_CYCLES_PER_SEC
	int
	default 120000000

config WDOG_INIT
	def_bool y
	# omit prompt to signify a "hidden" option
	help
	This processor enables the watchdog timer with a short timeout
	upon reset. Therefore, this requires that the watchdog be configured
	during reset handling.

config KERNEL_INIT_PRIORITY_DEFAULT
	default 40

config KERNEL_INIT_PRIORITY_DEVICE
	default 50

config UART_CONSOLE_PRIORITY
	default 60

if UART_K20

config UART_K20_PORT_0
	def_bool y

if UART_K20_PORT_0
config UART_K20_PORT_0_BASE_ADDR
	default 0x4006A000
config UART_K20_PORT_0_IRQ
	default 31
config UART_K20_PORT_0_IRQ_PRI
	default 3
config UART_K20_PORT_0_BAUD_RATE
	default 115200
config UART_K20_PORT_0_CLK_FREQ
	default 120000000
endif

config UART_K20_PORT_1
	def_bool y

if UART_K20_PORT_1
config UART_K20_PORT_1_BASE_ADDR
	default 0x4006B000
config UART_K20_PORT_1_IRQ
	default 33
config UART_K20_PORT_1_IRQ_PRI
	default 3
config UART_K20_PORT_1_BAUD_RATE
	default 115200
config UART_K20_PORT_1_CLK_FREQ
	default 120000000
endif

config UART_K20_PORT_2
	def_bool y
if UART_K20_PORT_2
config UART_K20_PORT_2_BASE_ADDR
	default 0x4006C000
config UART_K20_PORT_2_IRQ
	default 35
config UART_K20_PORT_2_IRQ_PRI
	default 3
config UART_K20_PORT_2_BAUD_RATE
	default 115200
config UART_K20_PORT_2_CLK_FREQ
	default 120000000
endif

config UART_K20_PORT_3
	def_bool y
if UART_K20_PORT_3
config UART_K20_PORT_3_BASE_ADDR
	default 0x4006D000
config UART_K20_PORT_3_IRQ
	default 37
config UART_K20_PORT_3_IRQ_PRI
	default 3
config UART_K20_PORT_3_BAUD_RATE
	default 115200
config UART_K20_PORT_3_CLK_FREQ
	default 120000000
endif

config UART_K20_PORT_4
	def_bool y
if UART_K20_PORT_4
config UART_K20_PORT_4_BASE_ADDR
	default 0x400EA000
config UART_K20_PORT_4_IRQ
	default 66
config UART_K20_PORT_4_IRQ_PRI
	default 3
config UART_K20_PORT_4_BAUD_RATE
	default 115200
config UART_K20_PORT_4_CLK_FREQ
	default 120000000
endif

endif # UART_K20

if UART_CONSOLE

config UART_CONSOLE_ON_DEV_NAME
	default "UART_0"

endif

if BLUETOOTH_UART

config BLUETOOTH_UART_ON_DEV_NAME
	default "UART_1"

endif

config GPIO
	def_bool y

if GPIO

config GPIO_K64
	def_bool y

config GPIO_K64_A
	def_bool y

config GPIO_K64_B
	def_bool y

config GPIO_K64_C
	def_bool y

config GPIO_K64_D
	def_bool y

config GPIO_K64_E
	def_bool y

endif

if GPIO_K64
config PORT_K64_BASE_ADDR
    default 0x40049000
endif

if GPIO_K64_A
config GPIO_K64_A_BASE_ADDR
    default 0x400FF000
endif

if GPIO_K64_B
config GPIO_K64_B_BASE_ADDR
    default 0x400FF040
endif

if GPIO_K64_C
config GPIO_K64_C_BASE_ADDR
    default 0x400FF080
endif

if GPIO_K64_D
config GPIO_K64_D_BASE_ADDR
    default 0x400FF0C0
endif

if GPIO_K64_E
config GPIO_K64_E_BASE_ADDR
    default 0x400FF100
endif

endif