60 lines
854 B
Text
60 lines
854 B
Text
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# Xtensa board configuration
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# Copyright (c) 2017 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_INTEL_APL_ADSP
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config SOC
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string
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default "intel_apl_adsp"
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config IRQ_OFFLOAD_INTNUM
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default 0
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# S1000 does not have MISC0.
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# Since EXCSAVE2 is unused by Zephyr, use it instead.
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config XTENSA_KERNEL_CPU_PTR_SR
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default "EXCSAVE2"
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config KERNEL_ENTRY
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default "_MainEntry"
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config MULTI_LEVEL_INTERRUPTS
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default y
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config 2ND_LEVEL_INTERRUPTS
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default y
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config DYNAMIC_INTERRUPTS
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default y
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config LOG
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default y
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if TEST
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# To prevent test uses TEST_LOGGING_MINIMAL
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config TEST_LOGGING_DEFAULTS
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default n
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endif # TEST
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if LOG
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config LOG_PRINTK
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default y
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config LOG_BACKEND_ADSP
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default y
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config LOG_BACKEND_ADSP_RINGBUF_BASE
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default "0xBE008000"
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config LOG_BACKEND_ADSP_RINGBUF_SIZE
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default "0x2000"
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endif # LOG
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endif
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