100 lines
3 KiB
C
100 lines
3 KiB
C
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/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MEC_PS2_H
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#define _MEC_PS2_H
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#include <stdint.h>
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#include <stddef.h>
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/*
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* PS2 TRX Buffer register
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* Writes -> Transmit buffer
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* Read <- Receive buffer
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*/
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#define MCHP_PS2_TRX_BUFF_REG_MASK 0xffu
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/* PS2 Control register */
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#define MCHP_PS2_CTRL_REG_MASK 0x3fu
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/* Select Transmit or Receive */
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#define MCHP_PS2_CTRL_TR_POS 0u
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#define MCHP_PS2_CTRL_TR_RX 0u
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#define MCHP_PS2_CTRL_TR_TX BIT(MCHP_PS2_CTRL_TR_POS)
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/* Enable PS2 state machine */
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#define MCHP_PS2_CTRL_EN_POS 1u
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#define MCHP_PS2_CTRL_EN BIT(MCHP_PS2_CTRL_EN_POS)
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/* Protocol parity selection */
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#define MCHP_PS2_CTRL_PAR_POS 2u
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#define MCHP_PS2_CTRL_PAR_MASK0 0x03u
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#define MCHP_PS2_CTRL_PAR_MASK 0x0cu
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#define MCHP_PS2_CTRL_PAR_ODD 0u
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#define MCHP_PS2_CTRL_PAR_EVEN 0x04u
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#define MCHP_PS2_CTRL_PAR_IGNORE 0x08u
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#define MCHP_PS2_CTRL_PAR_RSVD 0x0cu
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/* Protocol stop bit selection */
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#define MCHP_PS2_CTRL_STOP_POS 4u
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#define MCHP_PS2_CTRL_STOP_MASK0 0x03u
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#define MCHP_PS2_CTRL_STOP_MASK 0x30u
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#define MCHP_PS2_CTRL_STOP_ACT_HI 0u
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#define MCHP_PS2_CTRL_STOP_ACT_LO 0x10u
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#define MCHP_PS2_CTRL_STOP_IGNORE 0x20u
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#define MCHP_PS2_CTRL_STOP_RSVD 0x30u
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/* PS2 Status register */
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#define MCHP_PS2_STATUS_REG_MASK 0xffu
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#define MCHP_PS2_STATUS_RW1C_MASK 0xaeu
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#define MCHP_PS2_STATUS_RO_MASK 0x51u
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/* RX Data Ready(Read-Only) */
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#define MCHP_PS2_STATUS_RXD_RDY_POS 0
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#define MCHP_PS2_STATUS_RXD_RDY BIT(MCHP_PS2_STATUS_RXD_RDY_POS)
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/* RX Timeout(R/W1C) */
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#define MCHP_PS2_STATUS_RX_TMOUT_POS 1
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#define MCHP_PS2_STATUS_RX_TMOUT BIT(MCHP_PS2_STATUS_RX_TMOUT_POS)
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/* Parity Error(R/W1C) */
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#define MCHP_PS2_STATUS_PE_POS 2
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#define MCHP_PS2_STATUS_PE BIT(MCHP_PS2_STATUS_PE_POS)
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/* Framing Error(R/W1C) */
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#define MCHP_PS2_STATUS_FE_POS 3
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#define MCHP_PS2_STATUS_FE BIT(MCHP_PS2_STATUS_FE_POS)
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/* Transmitter is Idle(Read-Only) */
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#define MCHP_PS2_STATUS_TX_IDLE_POS 4
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#define MCHP_PS2_STATUS_TX_IDLE BIT(MCHP_PS2_STATUS_TX_IDLE_POS)
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/* Transmitter timeout(R/W1C) */
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#define MCHP_PS2_STATUS_TX_TMOUT_POS 5
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#define MCHP_PS2_STATUS_TX_TMOUT BIT(MCHP_PS2_STATUS_TX_TMOUT_POS)
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/* RX is Busy(Read-Only) */
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#define MCHP_PS2_STATUS_RX_BUSY_POS 6
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#define MCHP_PS2_STATUS_RX_BUSY BIT(MCHP_PS2_STATUS_RX_BUSY_POS)
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/* Transmitter start timeout(R/W1C) */
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#define MCHP_PS2_STATUS_TX_ST_TMOUT_POS 7
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#define MCHP_PS2_STATUS_TX_ST_TMOUT BIT(MCHP_PS2_STATUS_TX_ST_TMOUT_POS)
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/* PS2 Protocol bit positions */
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#define MCHP_PS2_PROT_START_BIT_POS 1
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#define MCHP_PS2_PROT_DATA_BIT0_POS 2
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#define MCHP_PS2_PROT_DATA_BIT1_POS 3
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#define MCHP_PS2_PROT_DATA_BIT2_POS 4
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#define MCHP_PS2_PROT_DATA_BIT3_POS 5
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#define MCHP_PS2_PROT_DATA_BIT4_POS 6
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#define MCHP_PS2_PROT_DATA_BIT5_POS 7
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#define MCHP_PS2_PROT_DATA_BIT6_POS 8
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#define MCHP_PS2_PROT_DATA_BIT7_POS 9
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#define MCHP_PS2_PROT_PARITY_POS 10
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#define MCHP_PS2_PROT_STOP_BIT_POS 11
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/** @brief PS/2 controller */
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struct ps2_regs {
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volatile uint32_t TRX_BUFF;
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volatile uint32_t CTRL;
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volatile uint32_t STATUS;
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};
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#endif /* #ifndef _MEC_PS2_H */
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