michaelh/zephyr
1
0
Fork 0
Code Releases Activity
zephyr/arch/x86/platforms/quark_se/Makefile

10 lines
313 B
Makefile
Raw Normal View History

x86: add support for the Quark SE platform Intel Quark SE Microcontroller with an onboard sensor subsystem. Processor * Intel Quark SE Processor Core * Intel Pentium® Processor-based x86 ISA compatible CPU * 32MHz clock, 32-bit address bus * 8kB 2-way L1 instruction cache Memory * 384kB of on-die NVM +8kB OTP on-die NVM * 80kB of on-die SRAM Change-Id: I849ec5c1f1639e10a48c9ebab7d3653b88b23eb7 Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-11-21 22:25:41 -05:00
ccflags-y +=-I$(srctree)/arch/x86
build: set platform name without quotes and reuse everywhere Avoid having to remove quotes wherever the platform name is used by exporting the variable only once. Change-Id: I4cb51901e4ac19d70d0310fe6bbacd157f586661 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-11-26 16:45:36 -05:00
ccflags-y +=-I$(srctree)/arch/x86/platforms/$(PLATFORM_NAME)/
x86: add support for the Quark SE platform Intel Quark SE Microcontroller with an onboard sensor subsystem. Processor * Intel Quark SE Processor Core * Intel Pentium® Processor-based x86 ISA compatible CPU * 32MHz clock, 32-bit address bus * 8kB 2-way L1 instruction cache Memory * 384kB of on-die NVM +8kB OTP on-die NVM * 80kB of on-die SRAM Change-Id: I849ec5c1f1639e10a48c9ebab7d3653b88b23eb7 Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-11-21 22:25:41 -05:00
ccflags-y +=-I$(srctree)/include/drivers
ccflags-y +=-I$(srctree)/drivers
asflags-y := ${ccflags-y}
quark_se: apic: work around EOI forwarding issue Quark SE Lakemont core has a hardware bug where the LOAPIC does not properly notify the IOAPIC to clear the IRR bit for level- triggered interrupts. This patch introduces a workaround where the vector ID of the in-service interrupt is manually written to the IOAPIC_EOI register, resulting in the bit being cleared. Unfortunately, in the context where EOI happens it's very difficult to identify which IRQ line is being serviced, so this is done unconditionally for all interrupts vectors whether they are registered in the IOAPIC RTE table or not. Change-Id: I639cd258dec4f50934e17eadbb821e6a7112e636 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-12-10 14:43:10 -08:00
obj-y = system.o quark_se_config.o eoi.o
x86: add support for the Quark SE platform Intel Quark SE Microcontroller with an onboard sensor subsystem. Processor * Intel Quark SE Processor Core * Intel Pentium® Processor-based x86 ISA compatible CPU * 32MHz clock, 32-bit address bus * 8kB 2-way L1 instruction cache Memory * 384kB of on-die NVM +8kB OTP on-die NVM * 80kB of on-die SRAM Change-Id: I849ec5c1f1639e10a48c9ebab7d3653b88b23eb7 Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-11-21 22:25:41 -05:00
obj-$(CONFIG_PINMUX) += pinmux.o
obj-$(CONFIG_PINMUX) += curie101_pinmux.o
Copy permalink