2019-04-10 00:43:42 -07:00
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/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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2019-06-25 15:53:52 -04:00
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#include <drivers/gpio.h>
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2019-04-10 00:43:42 -07:00
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#include <soc.h>
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#include "gpio_utils.h"
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static const u32_t valid_ctrl_masks[NUM_MCHP_GPIO_PORTS] = {
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(MCHP_GPIO_PORT_A_BITMAP),
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(MCHP_GPIO_PORT_B_BITMAP),
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(MCHP_GPIO_PORT_C_BITMAP),
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(MCHP_GPIO_PORT_D_BITMAP),
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(MCHP_GPIO_PORT_E_BITMAP),
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(MCHP_GPIO_PORT_F_BITMAP)
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};
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struct gpio_xec_data {
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2019-09-20 07:36:21 -05:00
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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2019-04-10 00:43:42 -07:00
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/* port ISR callback routine address */
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sys_slist_t callbacks;
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/* pin callback routine enable flags, by pin number */
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u32_t pin_callback_enables;
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};
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struct gpio_xec_config {
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__IO u32_t *pcr1_base;
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u8_t girq_id;
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u32_t port_num;
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u32_t flags;
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};
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static int gpio_xec_configure(struct device *dev,
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2019-08-02 11:31:51 +02:00
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int access_op, u32_t pin, int flags)
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2019-04-10 00:43:42 -07:00
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{
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const struct gpio_xec_config *config = dev->config->config_info;
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__IO u32_t *current_pcr1;
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u32_t pcr1 = 0;
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u32_t mask = 0;
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u32_t gpio_interrupt = 0;
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/* Validate pin number range in terms of current port */
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2019-08-02 11:31:51 +02:00
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if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0) {
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2019-04-10 00:43:42 -07:00
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return -EINVAL;
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2019-08-02 11:31:51 +02:00
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}
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2019-04-10 00:43:42 -07:00
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/* Check for an invalid pin configuration */
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if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
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return -EINVAL;
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}
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/* Check if GPIO port supports interrupts */
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if ((flags & GPIO_INT) && ((config->flags & GPIO_INT) == 0)) {
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return -EINVAL;
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}
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/* The flags contain options that require touching registers in the
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* PCRs for a given GPIO. There are no GPIO modules in Microchip SOCs!
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*
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* Start with the GPIO module and set up the pin direction register.
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* 0 - pin is input, 1 - pin is output
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*/
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mask |= MCHP_GPIO_CTRL_DIR_MASK;
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2019-09-26 18:22:34 -07:00
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mask |= MCHP_GPIO_CTRL_INPAD_DIS_MASK;
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2019-04-10 00:43:42 -07:00
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
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pcr1 &= ~BIT(MCHP_GPIO_CTRL_DIR_POS);
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} else { /* GPIO_DIR_OUT */
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pcr1 |= BIT(MCHP_GPIO_CTRL_DIR_POS);
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}
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} else { /* GPIO_ACCESS_BY_PORT is not supported */
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return -EINVAL;
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}
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/* Figure out the pullup/pulldown configuration and keep it in the
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* pcr1 variable
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*/
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mask |= MCHP_GPIO_CTRL_PUD_MASK;
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if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
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/* Enable the pull and select the pullup resistor. */
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pcr1 |= MCHP_GPIO_CTRL_PUD_PU;
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} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN) {
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/* Enable the pull and select the pulldown resistor */
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pcr1 |= MCHP_GPIO_CTRL_PUD_PD;
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}
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/* Assemble mask for level/edge triggered interrrupts */
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mask |= MCHP_GPIO_CTRL_IDET_MASK;
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if (flags & GPIO_INT) {
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if (flags & GPIO_INT_EDGE) {
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/* Enable edge interrupts */
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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gpio_interrupt = MCHP_GPIO_CTRL_IDET_REDGE;
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} else if (flags & GPIO_INT_DOUBLE_EDGE) {
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gpio_interrupt = MCHP_GPIO_CTRL_IDET_BEDGE;
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} else {
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gpio_interrupt = MCHP_GPIO_CTRL_IDET_FEDGE;
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}
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} else { /* GPIO_INT_LEVEL */
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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gpio_interrupt = MCHP_GPIO_CTRL_IDET_LVL_HI;
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} else {
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gpio_interrupt = MCHP_GPIO_CTRL_IDET_LVL_LO;
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}
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}
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pcr1 |= gpio_interrupt;
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/* We enable the interrupts in the EC aggregator so that the
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* result can be forwarded to the ARM NVIC
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*/
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MCHP_GIRQ_ENSET(config->girq_id) = BIT(pin);
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} else {
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/* Explicitly disable interrupts, otherwise the configuration
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* results in level triggered/low interrupts
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*/
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pcr1 |= MCHP_GPIO_CTRL_IDET_DISABLE;
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}
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/* Use Gpio output register for writing in order to have simetry with
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* respect of Gpio input
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*/
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mask |= MCHP_GPIO_CTRL_AOD_MASK;
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pcr1 |= MCHP_GPIO_CTRL_AOD_MASK;
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/* Now write contents of pcr1 variable to the PCR1 register that
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* corresponds to the GPIO being configured
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*/
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current_pcr1 = config->pcr1_base + pin;
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*current_pcr1 = (*current_pcr1 & ~mask) | pcr1;
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return 0;
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}
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static int gpio_xec_write(struct device *dev,
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2019-08-02 11:31:51 +02:00
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int access_op, u32_t pin, u32_t value)
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{
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const struct gpio_xec_config *config = dev->config->config_info;
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u32_t port_n = config->port_num;
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/* GPIO output registers are used for writing */
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__IO u32_t *gpio_base = (__IO u32_t *)(GPIO_PAROUT_BASE
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+ (port_n << 2));
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (value) {
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/* Set the data output for the corresponding pin.
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* Writing zeros to the other bits leaves the data
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* output unchanged for the other pins
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*/
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*gpio_base |= BIT(pin);
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} else {
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/* Clear the data output for the corresponding pin.
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* Writing zeros to the other bits leaves the data
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* output unchanged for the other pins
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*/
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*gpio_base &= ~BIT(pin);
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}
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} else { /* GPIO_ACCESS_BY_PORT not supported */
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return -EINVAL;
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}
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return 0;
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}
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static int gpio_xec_read(struct device *dev,
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2019-08-02 11:31:51 +02:00
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int access_op, u32_t pin, u32_t *value)
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2019-04-10 00:43:42 -07:00
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{
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const struct gpio_xec_config *config = dev->config->config_info;
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u32_t port_n = config->port_num;
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/* GPIO input registers are used for reading */
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__IO u32_t *gpio_base = (__IO u32_t *)(GPIO_PARIN_BASE + (port_n << 2));
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*value = *gpio_base;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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*value = (*value & BIT(pin)) >> pin;
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} else { /* GPIO_ACCESS_BY_PORT not supported */
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return -EINVAL;
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}
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return 0;
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}
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static int gpio_xec_manage_callback(struct device *dev,
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2019-08-02 11:31:51 +02:00
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struct gpio_callback *callback, bool set)
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2019-04-10 00:43:42 -07:00
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{
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struct gpio_xec_data *data = dev->driver_data;
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gpio_manage_callback(&data->callbacks, callback, set);
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return 0;
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}
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static int gpio_xec_enable_callback(struct device *dev,
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2019-08-02 11:31:51 +02:00
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int access_op, u32_t pin)
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2019-04-10 00:43:42 -07:00
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{
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struct gpio_xec_data *data = dev->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->pin_callback_enables |= BIT(pin);
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} else { /* GPIO_ACCESS_BY_PORT not supported */
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return -EINVAL;
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}
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return 0;
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}
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static int gpio_xec_disable_callback(struct device *dev,
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2019-08-02 11:31:51 +02:00
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int access_op, u32_t pin)
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{
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struct gpio_xec_data *data = dev->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->pin_callback_enables &= ~BIT(pin);
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} else { /* GPIO_ACCESS_BY_PORT not supported */
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return -EINVAL;
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}
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return 0;
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}
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static void gpio_gpio_xec_port_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct gpio_xec_config *config = dev->config->config_info;
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struct gpio_xec_data *data = dev->driver_data;
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u32_t girq_result;
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u32_t enabled_int;
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/* Figure out which interrupts have been triggered from the EC
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* aggregator result register
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*/
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girq_result = MCHP_GIRQ_RESULT(config->girq_id);
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enabled_int = girq_result & data->pin_callback_enables;
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/* Clear source register in aggregator before firing callbacks */
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REG32(MCHP_GIRQ_SRC_ADDR(config->girq_id)) = girq_result;
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gpio_fire_callbacks(&data->callbacks, dev, enabled_int);
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}
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static const struct gpio_driver_api gpio_xec_driver_api = {
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.config = gpio_xec_configure,
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.write = gpio_xec_write,
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.read = gpio_xec_read,
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.manage_callback = gpio_xec_manage_callback,
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.enable_callback = gpio_xec_enable_callback,
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.disable_callback = gpio_xec_disable_callback,
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};
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#ifdef CONFIG_GPIO_XEC_GPIO000_036
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static int gpio_xec_port000_036_init(struct device *dev);
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static const struct gpio_xec_config gpio_xec_port000_036_config = {
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.pcr1_base = (u32_t *) DT_GPIO_XEC_GPIO000_036_BASE_ADDR,
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.port_num = MCHP_GPIO_000_036,
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#ifdef DT_GPIO_XEC_GPIO000_036_IRQ
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.girq_id = MCHP_GIRQ11_ID,
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.flags = GPIO_INT,
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#else
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.flags = 0,
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#endif
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};
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static struct gpio_xec_data gpio_xec_port000_036_data;
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DEVICE_AND_API_INIT(gpio_xec_port000_036, DT_GPIO_XEC_GPIO000_036_LABEL,
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gpio_xec_port000_036_init,
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&gpio_xec_port000_036_data, &gpio_xec_port000_036_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_xec_driver_api);
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static int gpio_xec_port000_036_init(struct device *dev)
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{
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#ifdef DT_GPIO_XEC_GPIO000_036_IRQ
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const struct gpio_xec_config *config = dev->config->config_info;
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/* Turn on the block enable in the EC aggregator */
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MCHP_GIRQ_BLK_SETEN(config->girq_id);
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IRQ_CONNECT(DT_GPIO_XEC_GPIO000_036_IRQ,
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DT_GPIO_XEC_GPIO000_036_IRQ_PRIORITY,
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gpio_gpio_xec_port_isr, DEVICE_GET(gpio_xec_port000_036), 0);
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irq_enable(DT_GPIO_XEC_GPIO000_036_IRQ);
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#endif
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return 0;
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}
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#endif /* CONFIG_GPIO_XEC_GPIO000_036 */
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#ifdef CONFIG_GPIO_XEC_GPIO040_076
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static int gpio_xec_port040_076_init(struct device *dev);
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static const struct gpio_xec_config gpio_xec_port040_076_config = {
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.pcr1_base = (u32_t *) DT_GPIO_XEC_GPIO040_076_BASE_ADDR,
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.port_num = MCHP_GPIO_040_076,
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#ifdef DT_GPIO_XEC_GPIO040_076_IRQ
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.girq_id = MCHP_GIRQ10_ID,
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.flags = GPIO_INT,
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#else
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.flags = 0,
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#endif
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};
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static struct gpio_xec_data gpio_xec_port040_076_data;
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DEVICE_AND_API_INIT(gpio_xec_port040_076, DT_GPIO_XEC_GPIO040_076_LABEL,
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gpio_xec_port040_076_init,
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&gpio_xec_port040_076_data, &gpio_xec_port040_076_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_xec_driver_api);
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static int gpio_xec_port040_076_init(struct device *dev)
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{
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#ifdef DT_GPIO_XEC_GPIO040_076_IRQ
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const struct gpio_xec_config *config = dev->config->config_info;
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/* Turn on the block enable in the EC aggregator */
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MCHP_GIRQ_BLK_SETEN(config->girq_id);
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IRQ_CONNECT(DT_GPIO_XEC_GPIO040_076_IRQ,
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DT_GPIO_XEC_GPIO040_076_IRQ_PRIORITY,
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gpio_gpio_xec_port_isr, DEVICE_GET(gpio_xec_port040_076), 0);
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irq_enable(DT_GPIO_XEC_GPIO040_076_IRQ);
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#endif
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return 0;
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}
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#endif /* CONFIG_GPIO_XEC_GPIO040_076 */
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#ifdef CONFIG_GPIO_XEC_GPIO100_136
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static int gpio_xec_port100_136_init(struct device *dev);
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static const struct gpio_xec_config gpio_xec_port100_136_config = {
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.pcr1_base = (u32_t *) DT_GPIO_XEC_GPIO100_136_BASE_ADDR,
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.port_num = MCHP_GPIO_100_136,
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#ifdef DT_GPIO_XEC_GPIO100_136_IRQ
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.girq_id = MCHP_GIRQ09_ID,
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.flags = GPIO_INT,
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#else
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.flags = 0,
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#endif
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};
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static struct gpio_xec_data gpio_xec_port100_136_data;
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DEVICE_AND_API_INIT(gpio_xec_port100_136, DT_GPIO_XEC_GPIO100_136_LABEL,
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gpio_xec_port100_136_init,
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&gpio_xec_port100_136_data, &gpio_xec_port100_136_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_xec_driver_api);
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static int gpio_xec_port100_136_init(struct device *dev)
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{
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#ifdef DT_GPIO_XEC_GPIO100_136_IRQ
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const struct gpio_xec_config *config = dev->config->config_info;
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/* Turn on the block enable in the EC aggregator */
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MCHP_GIRQ_BLK_SETEN(config->girq_id);
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IRQ_CONNECT(DT_GPIO_XEC_GPIO100_136_IRQ,
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DT_GPIO_XEC_GPIO100_136_IRQ_PRIORITY,
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gpio_gpio_xec_port_isr, DEVICE_GET(gpio_xec_port100_136), 0);
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irq_enable(DT_GPIO_XEC_GPIO100_136_IRQ);
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#endif
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return 0;
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}
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#endif /* CONFIG_GPIO_XEC_GPIO100_136 */
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#ifdef CONFIG_GPIO_XEC_GPIO140_176
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static int gpio_xec_port140_176_init(struct device *dev);
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static const struct gpio_xec_config gpio_xec_port140_176_config = {
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.pcr1_base = (u32_t *) DT_GPIO_XEC_GPIO140_176_BASE_ADDR,
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.port_num = MCHP_GPIO_140_176,
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#ifdef DT_GPIO_XEC_GPIO140_176_IRQ
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.girq_id = MCHP_GIRQ08_ID,
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.flags = GPIO_INT,
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#else
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.flags = 0,
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#endif
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};
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static struct gpio_xec_data gpio_xec_port140_176_data;
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DEVICE_AND_API_INIT(gpio_xec_port140_176, DT_GPIO_XEC_GPIO140_176_LABEL,
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gpio_xec_port140_176_init,
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&gpio_xec_port140_176_data, &gpio_xec_port140_176_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_xec_driver_api);
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static int gpio_xec_port140_176_init(struct device *dev)
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{
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#ifdef DT_GPIO_XEC_GPIO140_176_IRQ
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const struct gpio_xec_config *config = dev->config->config_info;
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/* Turn on the block enable in the EC aggregator */
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MCHP_GIRQ_BLK_SETEN(config->girq_id);
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IRQ_CONNECT(DT_GPIO_XEC_GPIO140_176_IRQ,
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DT_GPIO_XEC_GPIO140_176_IRQ_PRIORITY,
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gpio_gpio_xec_port_isr, DEVICE_GET(gpio_xec_port140_176), 0);
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irq_enable(DT_GPIO_XEC_GPIO140_176_IRQ);
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#endif
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return 0;
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}
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#endif /* CONFIG_GPIO_XEC_GPIO140_176 */
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#ifdef CONFIG_GPIO_XEC_GPIO200_236
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static int gpio_xec_port200_236_init(struct device *dev);
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static const struct gpio_xec_config gpio_xec_port200_236_config = {
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.pcr1_base = (u32_t *) DT_GPIO_XEC_GPIO200_236_BASE_ADDR,
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.port_num = MCHP_GPIO_200_236,
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#ifdef DT_GPIO_XEC_GPIO200_236_IRQ
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.girq_id = MCHP_GIRQ12_ID,
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.flags = GPIO_INT,
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#else
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.flags = 0,
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#endif
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};
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static struct gpio_xec_data gpio_xec_port200_236_data;
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DEVICE_AND_API_INIT(gpio_xec_port200_236, DT_GPIO_XEC_GPIO200_236_LABEL,
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gpio_xec_port200_236_init,
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&gpio_xec_port200_236_data, &gpio_xec_port200_236_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_xec_driver_api);
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static int gpio_xec_port200_236_init(struct device *dev)
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{
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#ifdef DT_GPIO_XEC_GPIO200_236_IRQ
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const struct gpio_xec_config *config = dev->config->config_info;
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/* Turn on the block enable in the EC aggregator */
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MCHP_GIRQ_BLK_SETEN(config->girq_id);
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IRQ_CONNECT(DT_GPIO_XEC_GPIO200_236_IRQ,
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DT_GPIO_XEC_GPIO200_236_IRQ_PRIORITY,
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gpio_gpio_xec_port_isr, DEVICE_GET(gpio_xec_port200_236), 0);
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irq_enable(DT_GPIO_XEC_GPIO200_236_IRQ);
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#endif
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return 0;
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}
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#endif /* CONFIG_GPIO_XEC_GPIO200_236 */
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#ifdef CONFIG_GPIO_XEC_GPIO240_276
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static int gpio_xec_port240_276_init(struct device *dev);
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static const struct gpio_xec_config gpio_xec_port240_276_config = {
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.pcr1_base = (u32_t *) DT_GPIO_XEC_GPIO240_276_BASE_ADDR,
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.port_num = MCHP_GPIO_240_276,
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#ifdef DT_GPIO_XEC_GPIO240_276_IRQ
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.girq_id = MCHP_GIRQ26_ID,
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.flags = GPIO_INT,
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#else
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.flags = 0,
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#endif
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};
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static struct gpio_xec_data gpio_xec_port240_276_data;
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DEVICE_AND_API_INIT(gpio_xec_port240_276, DT_GPIO_XEC_GPIO240_276_LABEL,
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gpio_xec_port240_276_init,
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&gpio_xec_port240_276_data, &gpio_xec_port240_276_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_xec_driver_api);
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static int gpio_xec_port240_276_init(struct device *dev)
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{
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#ifdef DT_GPIO_XEC_GPIO240_276_IRQ
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const struct gpio_xec_config *config = dev->config->config_info;
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/* Turn on the block enable in the EC aggregator */
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MCHP_GIRQ_BLK_SETEN(config->girq_id);
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IRQ_CONNECT(DT_GPIO_XEC_GPIO240_276_IRQ,
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DT_GPIO_XEC_GPIO240_276_IRQ_PRIORITY,
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gpio_gpio_xec_port_isr, DEVICE_GET(gpio_xec_port240_276), 0);
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irq_enable(DT_GPIO_XEC_GPIO240_276_IRQ);
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#endif
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return 0;
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}
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#endif /* CONFIG_GPIO_XEC_GPIO240_276 */
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