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zephyr/soc/xtensa/esp32/Kconfig.soc

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arch: xtensa: Add ESP32 SoC Due to the configurable nature of the Xtensa platform, the generic name of "LX6" cannot be used to describe an SoC as far as Zephyr goes. So ESP32 is defined both as a SoC and as a board. This is based on work by Rajavardhan Gundi. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-05-03 14:28:12 -07:00
# Copyright (c) 2017 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_ESP32
bool "ESP32"
kconfig: Remove assignments to CONFIG_<arch> syms and hide them All board defconfig files currently set the architecture in addition to the board and the SoC, by setting e.g. CONFIG_ARM=y. This spams up defconfig files. CONFIG_<arch> symbols currently being set in configuration files also means that they are configurable (can be changed in menuconfig and in configuration files), even though changing the architecture won't work, since other things get set from -DBOARD=<board>. Many boards also allow changing the architecture symbols independently from the SoC symbols, which doesn't make sense. Get rid of all assignments to CONFIG_<arch> symbols and clean up the relationships between symbols and the configuration interface, like this: 1. Remove the choice with the CONFIG_<arch> symbols in arch/Kconfig and turn the CONFIG_<arch> symbols into invisible (promptless/nonconfigurable) symbols instead. Getting rid of the choice allows the symbols to be 'select'ed (choice symbols don't support 'select'). 2. Select the right CONFIG_<arch> symbol from the SOC_SERIES_* symbols. This makes sense since you know the architecture if you know the SoC. Put the select on the SOC_* symbol instead for boards that don't have a SOC_SERIES_*. 3. Remove all assignments to CONFIG_<arch> symbols. The assignments would generate errors now, since the symbols are promptless. The change was done by grepping for assignments to CONFIG_<arch> symbols, finding the SOC_SERIES_* (or SOC_*) symbol being set in the same defconfig file, and putting a 'select' on it instead. See https://github.com/ulfalizer/zephyr/commits/hide-arch-syms-unsquashed for a split-up version of this commit, which will make it easier to see how stuff was done. This needs to go in as one commit though. This change is safer than it might seem re. outstanding PRs, because any assignment to CONFIG_<arch> symbols generates an error now, making outdated stuff easy to catch. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-02-06 18:26:14 +01:00
select XTENSA
drivers: esp32/clock_control: Add Clock Driver - Support PLL for Higher Frequencies 80,160,240 MHz - Support XTAL Frequencies 26MHz, 40MHz - Clock Driver can't be disabled, because all of the other drivers will depend on it to get their operating Frequency based on chosen clock source (XTAL/PLL). - Add needed references to BBPLL i2c bus ROM functions. - Add `rtc` node to Device Tree. - Since All Peripherals Frequency is depending on CPU_CLK Source, `clock-source` property added to CPU node Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
2020-05-23 15:46:29 +02:00
select CLOCK_CONTROL
select CLOCK_CONTROL_ESP32
boards: esp32: add XIP support and enable bootloader build Disable RTC WDT enabled (by default) by 2nd stage bootloader in ESP-IDF. This WDT timer ensures correct hand-over and startup sequence from bootloader to application. Enabling bootloader caused system clock initialization to fail when clock rate is greater then 80MHz. This also fixes esp32 clock source code. Signed-off-by: Mahavir Jain <mahavir@espressif.com>
2020-08-03 20:23:18 +05:30
driver: esp32: add bluetooth support Add support to BLE and BR/EDR feature. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-04-01 00:51:49 -03:00
if SOC_ESP32
boards: esp32: add XIP support and enable bootloader build Disable RTC WDT enabled (by default) by 2nd stage bootloader in ESP-IDF. This WDT timer ensures correct hand-over and startup sequence from bootloader to application. Enabling bootloader caused system clock initialization to fail when clock rate is greater then 80MHz. This also fixes esp32 clock source code. Signed-off-by: Mahavir Jain <mahavir@espressif.com>
2020-08-03 20:23:18 +05:30
config IDF_TARGET_ESP32
bool "ESP32 as target board"
default y
config ESPTOOLPY_FLASHFREQ_80M
bool
default y
driver: esp32: add bluetooth support Add support to BLE and BR/EDR feature. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-04-01 00:51:49 -03:00
config ESP32_BT_RESERVE_DRAM
hex "Bluetooth controller reserved RAM region"
default 0xdb5c if BT
default 0
esp32: SPIRAM Support Adds SPIRAM support for ESP32 Configures k_heap for SPIRAM memory range Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
2020-12-03 18:44:56 +05:30
config ESP_SPIRAM
bool "Support for external, SPI-connected RAM"
help
This enables support for an external SPI RAM chip, connected in
parallel with the main SPI flash chip.
menu "SPI RAM config"
depends on ESP_SPIRAM
choice SPIRAM_TYPE
prompt "Type of SPI RAM chip in use"
default SPIRAM_TYPE_ESPPSRAM16
config SPIRAM_TYPE_ESPPSRAM16
bool "ESP-PSRAM16 or APS1604"
config SPIRAM_TYPE_ESPPSRAM32
bool "ESP-PSRAM32 or IS25WP032"
config SPIRAM_TYPE_ESPPSRAM64
bool "ESP-PSRAM64 or LY68L6400"
endchoice
config ESP_SPIRAM_SIZE
int "Size of SPIRAM part"
default 2097152 if SPIRAM_TYPE_ESPPSRAM16
default 4194304 if SPIRAM_TYPE_ESPPSRAM32
default 8388608 if SPIRAM_TYPE_ESPPSRAM64
help
Specify size of SPIRAM part.
NOTE: If SPIRAM size is greater than 4MB, only
lower 4MB can be allocated using k_malloc().
choice SPIRAM_SPEED
prompt "Set RAM clock speed"
default SPIRAM_SPEED_40M
help
Select the speed for the SPI RAM chip.
If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:
1. Flash SPI running at 40Mhz and RAM SPI running at 40Mhz
2. Flash SPI running at 80Mhz and RAM SPI running at 40Mhz
3. Flash SPI running at 80Mhz and RAM SPI running at 80Mhz
Note: If the third mode(80Mhz+80Mhz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host
will be occupied by the system. Which SPI host to use can be selected by the config item
SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The
option to select 80MHz will only be visible if the flash SPI speed is also 80MHz.
(ESPTOOLPY_FLASHFREQ_79M is true)
config SPIRAM_SPEED_40M
bool "40MHz clock speed"
config SPIRAM_SPEED_80M
depends on ESPTOOLPY_FLASHFREQ_80M
bool "80MHz clock speed"
endchoice
menu "PSRAM clock and cs IO for ESP32-DOWD"
config D0WD_PSRAM_CLK_IO
int "PSRAM CLK IO number"
range 0 33
default 17
help
The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
config D0WD_PSRAM_CS_IO
int "PSRAM CS IO number"
range 0 33
default 16
help
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
endmenu
menu "PSRAM clock and cs IO for ESP32-D2WD"
config D2WD_PSRAM_CLK_IO
int "PSRAM CLK IO number"
range 0 33
default 9
help
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
config D2WD_PSRAM_CS_IO
int "PSRAM CS IO number"
range 0 33
default 10
help
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
endmenu
menu "PSRAM clock and cs IO for ESP32-PICO"
config PICO_PSRAM_CS_IO
int "PSRAM CS IO number"
range 0 33
default 10
help
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
IO.
For the reference hardware design, please refer to
https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
endmenu
config SPIRAM_CUSTOM_SPIWP_SD3_PIN
bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5
default n
help
This setting is only used if the SPI flash pins have been overridden by setting the eFuses
SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.
When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
mode, so a WP pin setting is necessary.
If this config item is set to N (default), the correct WP pin will be automatically used for any
Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
to Y and specify the GPIO number connected to the WP pin.
When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
configured in the bootloader.
config SPIRAM_SPIWP_SD3_PIN
int "Custom SPI PSRAM WP(SD3) Pin"
range 0 33
default 7
help
The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
value to the GPIO number of the SPIRAM WP pin.
config SPIRAM
bool
default y
endmenu
endif # SOC_ESP32
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