2021-09-22 08:55:23 -05:00
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/*
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* Copyright (c) 2021 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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2022-11-11 12:55:56 +01:00
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#define DT_DRV_COMPAT nxp_pca9420
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2021-09-22 08:55:23 -05:00
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2022-11-14 15:43:45 +01:00
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#include <errno.h>
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2022-05-06 10:25:46 +02:00
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/i2c.h>
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2022-05-06 10:25:46 +02:00
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#include <zephyr/drivers/regulator.h>
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#include <zephyr/dt-bindings/regulator/pca9420.h>
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#include <zephyr/sys/linear_range.h>
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#include <zephyr/sys/util.h>
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2022-11-16 21:37:08 +01:00
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/** Register memory map. See datasheet for more details. */
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/** General purpose registers */
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/** @brief Top level system ctrl 0 */
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#define PCA9420_TOP_CNTL0 0x09U
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/** @brief Top level system ctrl 3 */
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#define PCA9420_TOP_CNTL3 0x0CU
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/** Regulator status indication registers */
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/** @brief Mode configuration for mode 0_0 */
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#define PCA9420_MODECFG_0_0 0x22U
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/** @brief Mode configuration for mode 0_1 */
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#define PCA9420_MODECFG_0_1 0x23U
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/** @brief Mode configuration for mode 0_2 */
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#define PCA9420_MODECFG_0_2 0x24U
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/** @brief Mode configuration for mode 0_3 */
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#define PCA9420_MODECFG_0_3 0x25U
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/** @brief VIN input current limit selection */
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#define PCA9420_TOP_CNTL0_VIN_ILIM_SEL_POS 5U
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#define PCA9420_TOP_CNTL0_VIN_ILIM_SEL_MASK 0xE0U
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#define PCA9420_TOP_CNTL0_VIN_ILIM_SEL_DISABLED 0x7U
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/** @brief I2C Mode control mask */
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#define PCA9420_TOP_CNTL3_MODE_I2C_POS 3U
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#define PCA9420_TOP_CNTL3_MODE_I2C_MASK 0x18U
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2022-11-16 21:37:08 +01:00
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/*
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* @brief Mode control selection mask. When this bit is set, the external
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* PMIC pins MODESEL0 and MODESEL1 can be used to select the active mode
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*/
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#define PCA9420_MODECFG_0_X_EN_MODE_SEL_BY_PIN 0x40U
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/*
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* @brief Mode configuration upon falling edge applied to ON pin. If set,
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* the device will switch to mode 0 when a valid falling edge is applied.
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* to the ON pin
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*/
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/** @brief Mode output voltage mask */
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#define PCA9420_MODECFG_0_SW1_OUT_MASK 0x3FU
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#define PCA9420_MODECFG_0_SW1_OUT_POS 0U
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/** @brief SW2_OUT offset and voltage level mask */
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#define PCA9420_MODECFG_1_SW2_OUT_MASK 0x3FU
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#define PCA9420_MODECFG_1_SW2_OUT_POS 0U
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/** @brief LDO1_OUT voltage level mask */
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#define PCA9420_MODECFG_2_LDO1_OUT_MASK 0xF0U
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#define PCA9420_MODECFG_2_LDO1_OUT_POS 4U
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/** @brief SW1 Enable */
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#define PCA9420_MODECFG_2_SW1_EN_MASK 0x08U
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#define PCA9420_MODECFG_2_SW1_EN_VAL 0x08U
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/** @brief SW2 Enable */
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#define PCA9420_MODECFG_2_SW2_EN_MASK 0x04U
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#define PCA9420_MODECFG_2_SW2_EN_VAL 0x04U
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/** @brief LDO1 Enable */
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#define PCA9420_MODECFG_2_LDO1_EN_MASK 0x02U
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#define PCA9420_MODECFG_2_LDO1_EN_VAL 0x02U
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/** @brief LDO2 Enable */
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#define PCA9420_MODECFG_2_LDO2_EN_MASK 0x01U
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#define PCA9420_MODECFG_2_LDO2_EN_VAL 0x01U
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/** @brief LDO2_OUT offset and voltage level mask */
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#define PCA9420_MODECFG_3_LDO2_OUT_MASK 0x3FU
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#define PCA9420_MODECFG_3_LDO2_OUT_POS 0U
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/** VIN ILIM resolution, uA/LSB */
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#define PCA9420_VIN_ILIM_UA_LSB 170000
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/** VIN ILIM minimum value, uA */
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#define PCA9420_VIN_ILIM_MIN_UA 85000
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/** Offset applied to MODECFG* registers for a given mode */
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#define PCA9420_MODECFG_OFFSET(mode) ((mode) * 4U)
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struct regulator_pca9420_desc {
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uint8_t enable_reg;
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uint8_t enable_mask;
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uint8_t enable_val;
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uint8_t vsel_reg;
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uint8_t vsel_mask;
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uint8_t vsel_pos;
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uint8_t num_ranges;
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const struct linear_range *ranges;
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};
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struct regulator_pca9420_common_config {
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struct i2c_dt_spec i2c;
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int32_t vin_ilim_ua;
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const uint8_t *allowed_modes;
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uint8_t allowed_modes_cnt;
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bool enable_modesel_pins;
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};
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struct regulator_pca9420_common_data {
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uint8_t mode;
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};
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struct regulator_pca9420_config {
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int32_t max_ua;
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bool enable_inverted;
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bool boot_on;
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const struct regulator_pca9420_desc *desc;
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const struct device *parent;
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};
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2022-11-29 16:00:06 +01:00
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struct regulator_pca9420_data {
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struct regulator_common_data data;
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};
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static const struct linear_range buck1_ranges[] = {
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LINEAR_RANGE_INIT(500000, 25000U, 0x0U, 0x28U),
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LINEAR_RANGE_INIT(1500000, 0U, 0x29U, 0x3E),
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LINEAR_RANGE_INIT(1800000, 0U, 0x3FU, 0x3FU),
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};
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static const struct linear_range buck2_ranges[] = {
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LINEAR_RANGE_INIT(1500000, 25000U, 0x0U, 0x18U),
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LINEAR_RANGE_INIT(2100000, 0U, 0x19U, 0x1F),
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LINEAR_RANGE_INIT(2700000, 25000U, 0x20U, 0x38U),
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LINEAR_RANGE_INIT(3300000, 0U, 0x39U, 0x3F),
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};
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static const struct linear_range ldo1_ranges[] = {
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LINEAR_RANGE_INIT(1700000, 25000U, 0x0U, 0x9U),
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LINEAR_RANGE_INIT(1900000, 0U, 0x9U, 0xFU),
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};
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static const struct linear_range ldo2_ranges[] = {
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LINEAR_RANGE_INIT(1500000, 25000U, 0x0U, 0x18U),
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LINEAR_RANGE_INIT(2100000, 0U, 0x19U, 0x1FU),
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LINEAR_RANGE_INIT(2700000, 25000U, 0x20U, 0x38U),
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LINEAR_RANGE_INIT(3300000, 0U, 0x39U, 0x3FU),
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};
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static const struct regulator_pca9420_desc buck1_desc = {
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.enable_reg = PCA9420_MODECFG_0_2,
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.enable_mask = PCA9420_MODECFG_2_SW1_EN_MASK,
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.enable_val = PCA9420_MODECFG_2_SW1_EN_VAL,
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.vsel_mask = PCA9420_MODECFG_0_SW1_OUT_MASK,
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.vsel_pos = PCA9420_MODECFG_0_SW1_OUT_POS,
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.vsel_reg = PCA9420_MODECFG_0_0,
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.ranges = buck1_ranges,
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.num_ranges = ARRAY_SIZE(buck1_ranges),
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};
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static const struct regulator_pca9420_desc buck2_desc = {
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.enable_reg = PCA9420_MODECFG_0_2,
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.enable_mask = PCA9420_MODECFG_2_SW2_EN_MASK,
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.enable_val = PCA9420_MODECFG_2_SW2_EN_VAL,
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.vsel_mask = PCA9420_MODECFG_1_SW2_OUT_MASK,
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.vsel_pos = PCA9420_MODECFG_1_SW2_OUT_POS,
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.vsel_reg = PCA9420_MODECFG_0_1,
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.ranges = buck2_ranges,
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.num_ranges = ARRAY_SIZE(buck2_ranges),
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};
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static const struct regulator_pca9420_desc ldo1_desc = {
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.enable_reg = PCA9420_MODECFG_0_2,
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.enable_mask = PCA9420_MODECFG_2_LDO1_EN_MASK,
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.enable_val = PCA9420_MODECFG_2_LDO1_EN_VAL,
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.vsel_mask = PCA9420_MODECFG_2_LDO1_OUT_MASK,
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.vsel_pos = PCA9420_MODECFG_2_LDO1_OUT_POS,
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.vsel_reg = PCA9420_MODECFG_0_2,
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.ranges = ldo1_ranges,
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.num_ranges = ARRAY_SIZE(ldo1_ranges),
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};
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static const struct regulator_pca9420_desc ldo2_desc = {
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.enable_reg = PCA9420_MODECFG_0_2,
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.enable_mask = PCA9420_MODECFG_2_LDO2_EN_MASK,
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.enable_val = PCA9420_MODECFG_2_LDO2_EN_VAL,
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.vsel_reg = PCA9420_MODECFG_0_3,
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.vsel_mask = PCA9420_MODECFG_3_LDO2_OUT_MASK,
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.vsel_pos = PCA9420_MODECFG_3_LDO2_OUT_POS,
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.ranges = ldo2_ranges,
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.num_ranges = ARRAY_SIZE(ldo2_ranges),
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};
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static bool regulator_pca9420_is_mode_allowed(const struct device *dev,
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uint8_t mode)
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{
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const struct regulator_pca9420_config *config = dev->config;
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const struct regulator_pca9420_common_config *cconfig = config->parent->config;
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for (uint8_t i = 0U; i < cconfig->allowed_modes_cnt; i++) {
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if (mode == cconfig->allowed_modes[i]) {
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return true;
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}
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}
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return false;
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}
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static int regulator_pca9420_get_voltage_mode(const struct device *dev,
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uint8_t mode, int32_t *voltage)
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{
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const struct regulator_pca9420_config *config = dev->config;
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const struct regulator_pca9420_common_config *cconfig = config->parent->config;
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int ret;
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uint8_t raw_reg;
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if (!regulator_pca9420_is_mode_allowed(dev, mode)) {
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return -ENOTSUP;
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}
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ret = i2c_reg_read_byte_dt(
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&cconfig->i2c,
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config->desc->vsel_reg + PCA9420_MODECFG_OFFSET(mode),
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&raw_reg);
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if (ret < 0) {
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return ret;
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}
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raw_reg = (raw_reg & config->desc->vsel_mask) >> config->desc->vsel_pos;
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return linear_range_group_get_value(config->desc->ranges,
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config->desc->num_ranges, raw_reg,
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voltage);
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}
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2022-11-30 15:27:52 +01:00
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static int regulator_set_voltage_mode(const struct device *dev,
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int32_t min_uv, int32_t max_uv,
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uint8_t mode)
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{
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const struct regulator_pca9420_config *config = dev->config;
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const struct regulator_pca9420_common_config *cconfig = config->parent->config;
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uint16_t idx;
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int ret;
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2022-11-30 15:27:52 +01:00
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if (!regulator_pca9420_is_mode_allowed(dev, mode)) {
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return -ENOTSUP;
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}
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2022-11-17 10:24:05 +01:00
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ret = linear_range_group_get_win_index(config->desc->ranges,
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config->desc->num_ranges, min_uv,
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max_uv, &idx);
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if (ret < 0) {
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return ret;
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}
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idx <<= config->desc->vsel_pos;
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2022-11-30 15:27:52 +01:00
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return i2c_reg_update_byte_dt(
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&cconfig->i2c,
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config->desc->vsel_reg + PCA9420_MODECFG_OFFSET(mode),
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config->desc->vsel_mask, (uint8_t)idx);
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}
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2022-12-01 11:14:21 +01:00
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static unsigned int regulator_pca9420_count_voltages(const struct device *dev)
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{
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const struct regulator_pca9420_config *config = dev->config;
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2022-01-19 11:00:48 +01:00
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2022-11-17 10:24:05 +01:00
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return linear_range_group_values_count(config->desc->ranges,
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config->desc->num_ranges);
|
2021-09-22 08:55:23 -05:00
|
|
|
}
|
|
|
|
|
2022-12-01 11:37:10 +01:00
|
|
|
static int regulator_pca9420_list_voltage(const struct device *dev,
|
|
|
|
unsigned int idx, int32_t *volt_uv)
|
2021-09-22 08:55:23 -05:00
|
|
|
{
|
2022-11-14 15:37:51 +01:00
|
|
|
const struct regulator_pca9420_config *config = dev->config;
|
2021-09-22 08:55:23 -05:00
|
|
|
|
2022-12-01 11:37:10 +01:00
|
|
|
return linear_range_group_get_value(config->desc->ranges,
|
|
|
|
config->desc->num_ranges, idx,
|
|
|
|
volt_uv);
|
2021-09-22 08:55:23 -05:00
|
|
|
}
|
|
|
|
|
2021-09-24 17:11:54 -05:00
|
|
|
/**
|
|
|
|
* Part of the extended regulator consumer API
|
|
|
|
* Sets the output voltage to the closest supported voltage value
|
|
|
|
*/
|
2022-11-11 13:53:11 +01:00
|
|
|
static int regulator_pca9420_set_voltage(const struct device *dev,
|
2022-11-11 14:04:11 +01:00
|
|
|
int32_t min_uv, int32_t max_uv)
|
2021-09-24 17:11:54 -05:00
|
|
|
{
|
2022-11-30 15:27:52 +01:00
|
|
|
const struct regulator_pca9420_config *config = dev->config;
|
|
|
|
struct regulator_pca9420_common_data *cdata = config->parent->data;
|
|
|
|
|
|
|
|
return regulator_set_voltage_mode(dev, min_uv, max_uv, cdata->mode);
|
2021-09-24 17:11:54 -05:00
|
|
|
}
|
|
|
|
|
2022-10-13 12:08:37 -05:00
|
|
|
|
2021-09-24 17:11:54 -05:00
|
|
|
/**
|
|
|
|
* Part of the extended regulator consumer API
|
|
|
|
* Gets the current output voltage in uV
|
|
|
|
*/
|
2022-12-01 13:23:32 +01:00
|
|
|
static int regulator_pca9420_get_voltage(const struct device *dev,
|
|
|
|
int32_t *volt_uv)
|
2021-09-24 17:11:54 -05:00
|
|
|
{
|
2022-11-30 15:27:52 +01:00
|
|
|
const struct regulator_pca9420_config *config = dev->config;
|
|
|
|
struct regulator_pca9420_common_data *cdata = config->parent->data;
|
2022-11-17 10:24:05 +01:00
|
|
|
|
2022-12-01 13:23:32 +01:00
|
|
|
return regulator_pca9420_get_voltage_mode(dev, cdata->mode, volt_uv);
|
2021-09-24 17:11:54 -05:00
|
|
|
}
|
|
|
|
|
2021-09-24 18:32:32 -05:00
|
|
|
/**
|
|
|
|
* Part of the extended regulator consumer API
|
|
|
|
* Gets the set current limit for the regulator
|
|
|
|
*/
|
2022-12-01 13:51:42 +01:00
|
|
|
static int regulator_pca9420_get_current_limit(const struct device *dev,
|
|
|
|
int32_t *curr_ua)
|
2021-09-24 18:32:32 -05:00
|
|
|
{
|
2022-11-14 15:37:51 +01:00
|
|
|
const struct regulator_pca9420_config *config = dev->config;
|
2022-11-17 12:30:43 +01:00
|
|
|
const struct regulator_pca9420_common_config *cconfig = config->parent->config;
|
2021-09-24 17:11:54 -05:00
|
|
|
|
2022-11-17 12:30:43 +01:00
|
|
|
if (cconfig->vin_ilim_ua == 0U) {
|
2022-12-01 13:51:42 +01:00
|
|
|
*curr_ua = config->max_ua;
|
|
|
|
} else {
|
|
|
|
*curr_ua = MIN(config->max_ua, cconfig->vin_ilim_ua);
|
2021-09-24 18:32:32 -05:00
|
|
|
}
|
2022-11-17 11:40:29 +01:00
|
|
|
|
2022-12-01 13:51:42 +01:00
|
|
|
return 0;
|
2021-09-24 18:32:32 -05:00
|
|
|
}
|
2021-09-22 08:55:23 -05:00
|
|
|
|
2022-11-11 12:55:56 +01:00
|
|
|
static int regulator_pca9420_set_mode(const struct device *dev, uint32_t mode)
|
2022-08-30 13:25:25 -05:00
|
|
|
{
|
2022-11-14 15:37:51 +01:00
|
|
|
const struct regulator_pca9420_config *config = dev->config;
|
2022-11-17 12:30:43 +01:00
|
|
|
const struct regulator_pca9420_common_config *cconfig = config->parent->config;
|
2022-11-30 15:27:52 +01:00
|
|
|
struct regulator_pca9420_common_data *cdata = config->parent->data;
|
|
|
|
int ret;
|
2022-08-30 13:25:25 -05:00
|
|
|
|
2022-12-01 13:46:49 +01:00
|
|
|
if (!regulator_pca9420_is_mode_allowed(dev, mode)) {
|
2022-08-30 13:25:25 -05:00
|
|
|
return -ENOTSUP;
|
|
|
|
}
|
|
|
|
|
2022-12-01 13:46:49 +01:00
|
|
|
/* change mode, to allow configuring voltage, but return -EPERM to
|
|
|
|
* indicate we are not really changing mode, as it is managed externally
|
|
|
|
*/
|
|
|
|
if (cconfig->enable_modesel_pins) {
|
|
|
|
cdata->mode = mode;
|
|
|
|
return -EPERM;
|
|
|
|
}
|
|
|
|
|
2022-11-30 15:27:52 +01:00
|
|
|
ret = i2c_reg_update_byte_dt(&cconfig->i2c, PCA9420_TOP_CNTL3,
|
|
|
|
mode << PCA9420_TOP_CNTL3_MODE_I2C_POS,
|
|
|
|
PCA9420_TOP_CNTL3_MODE_I2C_MASK);
|
|
|
|
if (ret < 0) {
|
|
|
|
return ret;
|
2022-08-30 13:25:25 -05:00
|
|
|
}
|
2022-11-30 15:27:52 +01:00
|
|
|
|
|
|
|
cdata->mode = mode;
|
|
|
|
|
|
|
|
return 0;
|
2022-08-30 13:25:25 -05:00
|
|
|
}
|
2021-09-22 08:55:23 -05:00
|
|
|
|
2022-11-29 16:00:06 +01:00
|
|
|
static int regulator_pca9420_enable(const struct device *dev)
|
2021-09-22 08:55:23 -05:00
|
|
|
{
|
2022-11-14 15:37:51 +01:00
|
|
|
const struct regulator_pca9420_config *config = dev->config;
|
2022-11-17 12:30:43 +01:00
|
|
|
const struct regulator_pca9420_common_config *cconfig = config->parent->config;
|
2022-11-29 16:00:06 +01:00
|
|
|
uint8_t en_val;
|
2021-09-22 08:55:23 -05:00
|
|
|
|
2022-11-16 21:37:08 +01:00
|
|
|
en_val = config->enable_inverted ? 0 : config->desc->enable_val;
|
2022-12-01 16:26:33 +01:00
|
|
|
return i2c_reg_update_byte_dt(&cconfig->i2c, config->desc->enable_reg,
|
|
|
|
config->desc->enable_mask, en_val);
|
2021-09-22 08:55:23 -05:00
|
|
|
}
|
|
|
|
|
2022-11-11 12:55:56 +01:00
|
|
|
static int regulator_pca9420_disable(const struct device *dev)
|
2021-09-22 08:55:23 -05:00
|
|
|
{
|
2022-11-14 15:37:51 +01:00
|
|
|
const struct regulator_pca9420_config *config = dev->config;
|
2022-11-17 12:30:43 +01:00
|
|
|
const struct regulator_pca9420_common_config *cconfig = config->parent->config;
|
2021-09-22 08:55:23 -05:00
|
|
|
uint8_t dis_val;
|
|
|
|
|
2022-11-29 16:00:06 +01:00
|
|
|
dis_val = config->enable_inverted ? config->desc->enable_val : 0;
|
2022-12-01 16:26:33 +01:00
|
|
|
return i2c_reg_update_byte_dt(&cconfig->i2c, config->desc->enable_reg,
|
|
|
|
config->desc->enable_mask, dis_val);
|
2021-09-22 08:55:23 -05:00
|
|
|
}
|
|
|
|
|
2022-11-14 15:37:51 +01:00
|
|
|
static int regulator_pca9420_init(const struct device *dev)
|
2021-09-22 08:55:23 -05:00
|
|
|
{
|
2022-11-14 15:37:51 +01:00
|
|
|
const struct regulator_pca9420_config *config = dev->config;
|
2022-10-13 13:11:20 -05:00
|
|
|
int rc = 0;
|
2021-09-22 08:55:23 -05:00
|
|
|
|
2022-11-29 16:00:06 +01:00
|
|
|
regulator_common_data_init(dev);
|
|
|
|
|
2022-11-17 12:30:43 +01:00
|
|
|
if (!device_is_ready(config->parent)) {
|
2021-09-22 08:55:23 -05:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
2022-11-17 12:30:43 +01:00
|
|
|
|
2022-10-13 13:11:20 -05:00
|
|
|
if (config->boot_on) {
|
2022-11-29 16:00:06 +01:00
|
|
|
rc = regulator_pca9420_enable(dev);
|
2022-10-13 13:11:20 -05:00
|
|
|
}
|
2022-11-30 15:27:52 +01:00
|
|
|
|
2022-10-13 13:11:20 -05:00
|
|
|
return rc;
|
2021-09-22 08:55:23 -05:00
|
|
|
}
|
|
|
|
|
2022-11-17 11:40:29 +01:00
|
|
|
static int regulator_pca9420_common_init(const struct device *dev)
|
|
|
|
{
|
|
|
|
const struct regulator_pca9420_common_config *config = dev->config;
|
2022-11-30 15:27:52 +01:00
|
|
|
const struct regulator_pca9420_common_data *data = dev->data;
|
2022-11-17 11:40:29 +01:00
|
|
|
uint8_t reg_val = PCA9420_TOP_CNTL0_VIN_ILIM_SEL_DISABLED;
|
2022-11-30 15:27:52 +01:00
|
|
|
int ret;
|
2022-11-17 11:40:29 +01:00
|
|
|
|
|
|
|
if (!device_is_ready(config->i2c.bus)) {
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2022-11-30 15:27:52 +01:00
|
|
|
if (config->enable_modesel_pins) {
|
|
|
|
/* enable MODESEL0/1 pins for each allowed mode */
|
|
|
|
for (uint8_t i = 0U; i < config->allowed_modes_cnt; i++) {
|
|
|
|
ret = i2c_reg_update_byte_dt(
|
|
|
|
&config->i2c,
|
|
|
|
PCA9420_MODECFG_0_0 +
|
|
|
|
PCA9420_MODECFG_OFFSET(config->allowed_modes[i]),
|
|
|
|
PCA9420_MODECFG_0_X_EN_MODE_SEL_BY_PIN,
|
|
|
|
PCA9420_MODECFG_0_X_EN_MODE_SEL_BY_PIN);
|
|
|
|
if (ret < 0) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ret = i2c_reg_update_byte_dt(
|
|
|
|
&config->i2c, PCA9420_TOP_CNTL3,
|
|
|
|
data->mode << PCA9420_TOP_CNTL3_MODE_I2C_POS,
|
|
|
|
PCA9420_TOP_CNTL3_MODE_I2C_MASK);
|
|
|
|
if (ret < 0) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-11-17 11:40:29 +01:00
|
|
|
/* configure VIN current limit */
|
|
|
|
if (config->vin_ilim_ua != 0U) {
|
|
|
|
reg_val = (config->vin_ilim_ua - PCA9420_VIN_ILIM_MIN_UA) /
|
|
|
|
PCA9420_VIN_ILIM_UA_LSB;
|
|
|
|
}
|
|
|
|
|
2022-12-01 16:26:33 +01:00
|
|
|
return i2c_reg_update_byte_dt(
|
2022-11-17 11:40:29 +01:00
|
|
|
&config->i2c, PCA9420_TOP_CNTL0,
|
|
|
|
PCA9420_TOP_CNTL0_VIN_ILIM_SEL_MASK,
|
|
|
|
reg_val << PCA9420_TOP_CNTL0_VIN_ILIM_SEL_POS);
|
|
|
|
}
|
|
|
|
|
2021-09-22 08:55:23 -05:00
|
|
|
|
|
|
|
static const struct regulator_driver_api api = {
|
2022-11-11 12:55:56 +01:00
|
|
|
.enable = regulator_pca9420_enable,
|
|
|
|
.disable = regulator_pca9420_disable,
|
|
|
|
.count_voltages = regulator_pca9420_count_voltages,
|
2022-12-01 11:37:10 +01:00
|
|
|
.list_voltage = regulator_pca9420_list_voltage,
|
2022-11-11 12:55:56 +01:00
|
|
|
.set_voltage = regulator_pca9420_set_voltage,
|
|
|
|
.get_voltage = regulator_pca9420_get_voltage,
|
|
|
|
.get_current_limit = regulator_pca9420_get_current_limit,
|
|
|
|
.set_mode = regulator_pca9420_set_mode,
|
2021-09-22 08:55:23 -05:00
|
|
|
};
|
|
|
|
|
2022-11-17 12:30:43 +01:00
|
|
|
#define REGULATOR_PCA9420_DEFINE(node_id, id, name, _parent) \
|
2022-11-16 16:27:08 +01:00
|
|
|
static struct regulator_pca9420_data data_##id; \
|
2022-11-14 12:37:55 +01:00
|
|
|
\
|
2022-11-16 16:27:08 +01:00
|
|
|
static const struct regulator_pca9420_config config_##id = { \
|
2022-11-17 11:40:29 +01:00
|
|
|
.max_ua = DT_PROP(node_id, regulator_max_microamp), \
|
2022-11-14 12:37:55 +01:00
|
|
|
.enable_inverted = DT_PROP(node_id, enable_inverted), \
|
2022-11-16 14:25:59 +01:00
|
|
|
.boot_on = DT_PROP(node_id, regulator_boot_on), \
|
2022-11-16 21:37:08 +01:00
|
|
|
.desc = &name ## _desc, \
|
2022-11-17 12:30:43 +01:00
|
|
|
.parent = _parent, \
|
2022-11-14 12:37:55 +01:00
|
|
|
}; \
|
|
|
|
\
|
2022-11-16 16:27:08 +01:00
|
|
|
DEVICE_DT_DEFINE(node_id, regulator_pca9420_init, NULL, &data_##id, \
|
|
|
|
&config_##id, POST_KERNEL, \
|
2022-11-14 12:37:55 +01:00
|
|
|
CONFIG_REGULATOR_PCA9420_INIT_PRIORITY, &api);
|
|
|
|
|
2022-11-17 12:30:43 +01:00
|
|
|
#define REGULATOR_PCA9420_DEFINE_COND(inst, child, parent) \
|
2022-11-16 16:27:08 +01:00
|
|
|
COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)), \
|
|
|
|
(REGULATOR_PCA9420_DEFINE(DT_INST_CHILD(inst, child), \
|
2022-11-17 12:30:43 +01:00
|
|
|
child ## inst, child, parent)), \
|
2022-11-17 11:40:29 +01:00
|
|
|
())
|
2022-11-14 12:37:55 +01:00
|
|
|
|
|
|
|
#define REGULATOR_PCA9420_DEFINE_ALL(inst) \
|
2022-11-30 15:27:52 +01:00
|
|
|
static const uint8_t allowed_modes_##inst[] = \
|
|
|
|
DT_INST_PROP(inst, regulator_allowed_modes); \
|
|
|
|
\
|
|
|
|
static struct regulator_pca9420_common_data data_##inst = { \
|
|
|
|
.mode = DT_INST_PROP(inst, regulator_initial_mode) \
|
|
|
|
}; \
|
2022-11-17 12:30:43 +01:00
|
|
|
\
|
2022-11-17 11:40:29 +01:00
|
|
|
static const struct regulator_pca9420_common_config config_##inst = { \
|
|
|
|
.i2c = I2C_DT_SPEC_INST_GET(inst), \
|
|
|
|
.vin_ilim_ua = DT_INST_PROP(inst, nxp_vin_ilim_microamp), \
|
2022-11-17 12:30:43 +01:00
|
|
|
.allowed_modes = allowed_modes_##inst, \
|
2022-11-30 15:27:52 +01:00
|
|
|
.allowed_modes_cnt = ARRAY_SIZE(allowed_modes_##inst), \
|
|
|
|
.enable_modesel_pins = \
|
|
|
|
DT_INST_PROP(inst, nxp_enable_modesel_pins), \
|
2022-11-17 11:40:29 +01:00
|
|
|
}; \
|
|
|
|
\
|
2022-11-30 15:27:52 +01:00
|
|
|
DEVICE_DT_INST_DEFINE(inst, regulator_pca9420_common_init, NULL, \
|
|
|
|
&data_##inst, &config_##inst, POST_KERNEL, \
|
2022-11-17 12:30:43 +01:00
|
|
|
CONFIG_REGULATOR_PCA9420_COMMON_INIT_PRIORITY, \
|
|
|
|
NULL); \
|
2022-11-17 11:40:29 +01:00
|
|
|
\
|
2022-11-17 12:30:43 +01:00
|
|
|
REGULATOR_PCA9420_DEFINE_COND(inst, buck1, DEVICE_DT_INST_GET(inst)) \
|
|
|
|
REGULATOR_PCA9420_DEFINE_COND(inst, buck2, DEVICE_DT_INST_GET(inst)) \
|
|
|
|
REGULATOR_PCA9420_DEFINE_COND(inst, ldo1, DEVICE_DT_INST_GET(inst)) \
|
|
|
|
REGULATOR_PCA9420_DEFINE_COND(inst, ldo2, DEVICE_DT_INST_GET(inst))
|
2022-11-14 12:37:55 +01:00
|
|
|
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(REGULATOR_PCA9420_DEFINE_ALL)
|