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zephyr/dts/arm/nxp/nxp_rt.dtsi

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arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/*
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/imx_ccm.h>
mimxrt1050_evk: Move led and button definitions to dts Moves the led and button definitions for the mimxrt1050_evk board from board.h to dts. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-14 13:52:45 -05:00
#include <dt-bindings/gpio/gpio.h>
dts: Add bindings for imx lpi2c Adds device tree bindings for the imx lpi2c peripheral. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-16 15:03:51 -06:00
#include <dt-bindings/i2c/i2c.h>
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/ {
dts: boards: Define dts aliases at soc level for i.mx rt socs Defines device tree aliases for on-chip peripherals at the soc level instead of the board level for all i.mx rt socs. The eliminates some duplicate code in the board level device trees, and will allow drivers to use device-tree generated macros directly instead of through dts fixups. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-10 09:56:56 -06:00
aliases {
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
eth = &enet;
dts: boards: Define dts aliases at soc level for i.mx rt socs Defines device tree aliases for on-chip peripherals at the soc level instead of the board level for all i.mx rt socs. The eliminates some duplicate code in the board level device trees, and will allow drivers to use device-tree generated macros directly instead of through dts fixups. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-10 09:56:56 -06:00
gpio-1 = &gpio1;
gpio-2 = &gpio2;
gpio-3 = &gpio3;
gpio-4 = &gpio4;
gpio-5 = &gpio5;
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
i2c-1 = &lpi2c1;
i2c-2 = &lpi2c2;
i2c-3 = &lpi2c3;
i2c-4 = &lpi2c4;
spi-1 = &lpspi1;
spi-2 = &lpspi2;
spi-3 = &lpspi3;
spi-4 = &lpspi4;
uart-1 = &lpuart1;
uart-2 = &lpuart2;
uart-3 = &lpuart3;
uart-4 = &lpuart4;
uart-5 = &lpuart5;
uart-6 = &lpuart6;
uart-7 = &lpuart7;
uart-8 = &lpuart8;
usbd-1 = &usb1;
usbd-2 = &usb2;
dts: boards: Define dts aliases at soc level for i.mx rt socs Defines device tree aliases for on-chip peripherals at the soc level instead of the board level for all i.mx rt socs. The eliminates some duplicate code in the board level device trees, and will allow drivers to use device-tree generated macros directly instead of through dts fixups. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-01-10 09:56:56 -06:00
};
drivers: entropy: replace CONFIG_ENTROPY_NAME with DT macro Replace CONFIG_ENTROPY_NAME with DT_CHOSEN_ZEPHYR_ENTROPY_LABEL. We now set zephyr,entropy in the chosen node of the device tree to the entropy device. This allows us to remove CONFIG_ENTROPY_NAME from dts_fixup.h. Also remove any other stale ENTROPY related defines in dts_fixup.h files. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-06 09:59:03 -05:00
chosen {
zephyr,entropy = &trng;
};
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m7";
reg = <0>;
soc: arm: add ARM MPU node info and fixup for Cortex-M7 SoCs Unlike Cortex-M3 and Cortex-M4, in Cortex-M7 the number of MPU regions may vary based on the implementation. This commit adds a DTS node for the ARM MPU peripheral in the device tree of Cortex-M7 SoCs and updates the fixup files, so we may extract the number of MPU regions at build time. SoCs: - nxp_rt - same70 - stm32f7 Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-05-14 09:00:10 +02:00
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv7m-mpu";
reg = <0xe000ed90 0x40>;
arm,num-mpu-regions = <16>;
};
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
};
};
dts: Add information about system bus frequency to the dts This commit adds a fixed clock node (representing clock driving system bus). The added node is then referenced by peripherals requiring information about driving clock frequency. Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-06-21 14:49:23 +02:00
sysclk: system-clock {
compatible = "fixed-clock";
clock-frequency = <600000000>;
#clock-cells = <0>;
};
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
soc {
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
flexram: flexram@400b0000 {
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
compatible = "nxp,imx-flexram";
reg = <0x400b0000 0x4000>;
interrupts = <38 0>;
#address-cells = <1>;
#size-cells = <1>;
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
itcm: itcm@0 {
dts: Rename imx-rt-{i,d}tcm compatible The imx-rt-{i,d}tcm bindings can actually be utilized on the i.MX6/7 as well for the TCM{L,U} regions of memory as they are specific to instruction or data. So let's rename imx-rt-{i,d}tcm to imx-{i,d}tcm. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-12-14 13:41:25 -06:00
compatible = "nxp,imx-itcm";
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
reg = <0x00000000 0x20000>;
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
dtcm: dtcm@20000000 {
dts: Rename imx-rt-{i,d}tcm compatible The imx-rt-{i,d}tcm bindings can actually be utilized on the i.MX6/7 as well for the TCM{L,U} regions of memory as they are specific to instruction or data. So let's rename imx-rt-{i,d}tcm to imx-{i,d}tcm. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-12-14 13:41:25 -06:00
compatible = "nxp,imx-dtcm";
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
reg = <0x20000000 0x20000>;
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
ocram: ocram@20200000 {
dts: Add binding for NXP i.MX RT itcm/dtcm memories Add comptiable into the device tree and associated binding files for NXP i.MX RT ITCM/DTCM memory regions. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-12-07 12:26:06 -06:00
compatible = "mmio-sram";
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
reg = <0x20200000 0x40000>;
};
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
flexspi: spi@402a8000 {
dts: mimxrt1050_evk: Add external memory nodes Adds flexspi and semc memory controllers to the i.MX RT SoC. Adds hyperflash, qspi, and sdram external memories to the mimxrt1050_evk board. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-04-04 18:32:32 -05:00
compatible = "nxp,imx-flexspi";
reg = <0x402a8000 0x4000>;
interrupts = <108 0>;
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
label = "FLEXSPI";
dts: mimxrt1050_evk: Add external memory nodes Adds flexspi and semc memory controllers to the i.MX RT SoC. Adds hyperflash, qspi, and sdram external memories to the mimxrt1050_evk board. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-04-04 18:32:32 -05:00
#address-cells = <1>;
boards: arm: nxp: imxrt: Fix SPI nodes on flexspi controller Fix the QSPI and hyperflash nodes to be proper SPI children and expose the address range for direct access as part of the controller's reg region. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-12-07 14:08:29 -06:00
#size-cells = <0>;
dts: mimxrt1050_evk: Add external memory nodes Adds flexspi and semc memory controllers to the i.MX RT SoC. Adds hyperflash, qspi, and sdram external memories to the mimxrt1050_evk board. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-04-04 18:32:32 -05:00
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
flexspi2: spi@402a4000 {
dts: arm: nxp_rt: add flexspi1 - Add info of flexspi1 Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-14 10:28:12 +08:00
compatible = "nxp,imx-flexspi";
reg = <0x402a4000 0x4000>;
interrupts = <107 0>;
label = "FLEXSPI1";
#address-cells = <1>;
#size-cells = <0>;
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
semc: semc0@402f0000 {
dts: mimxrt1050_evk: Add external memory nodes Adds flexspi and semc memory controllers to the i.MX RT SoC. Adds hyperflash, qspi, and sdram external memories to the mimxrt1050_evk board. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-04-04 18:32:32 -05:00
compatible = "nxp,imx-semc";
reg = <0x402f0000 0x4000>;
interrupts = <109 0>;
label = "SEMC0";
#address-cells = <1>;
#size-cells = <1>;
};
dts: arm: nxp_rt: Add GPT nodes i.MX RT chips have two GPT modules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-21 15:46:41 +01:00
gpt1: gpt@401ec000 {
compatible = "nxp,imx-gpt";
reg = <0x401ec000 0x4000>;
interrupts = <100 0>;
label = "GPT1";
};
gpt2: gpt@401f0000 {
compatible = "nxp,imx-gpt";
reg = <0x401f0000 0x4000>;
interrupts = <101 0>;
label = "GPT2";
};
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
ccm: ccm@400fc000 {
compatible = "nxp,imx-ccm";
reg = <0x400fc000 0x4000>;
label = "CCM";
dts/nxp: Fix dtc v1.4.6 warning: Missing property '#clock-cells' in node Replaces #clocks-cells with #clock-cell property in kinetis and i.mx rt socs. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-21 08:27:00 -05:00
#clock-cells = <3>;
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
};
gpio1: gpio@401b8000 {
compatible = "nxp,imx-gpio";
reg = <0x401b8000 0x4000>;
interrupts = <80 0>, <81 0>;
label = "GPIO_1";
mimxrt1050_evk: Move led and button definitions to dts Moves the led and button definitions for the mimxrt1050_evk board from board.h to dts. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-14 13:52:45 -05:00
gpio-controller;
#gpio-cells = <2>;
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
};
gpio2: gpio@401bc000 {
compatible = "nxp,imx-gpio";
reg = <0x401bc000 0x4000>;
interrupts = <82 0>, <83 0>;
label = "GPIO_2";
mimxrt1050_evk: Move led and button definitions to dts Moves the led and button definitions for the mimxrt1050_evk board from board.h to dts. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-14 13:52:45 -05:00
gpio-controller;
#gpio-cells = <2>;
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
};
gpio3: gpio@401c0000 {
compatible = "nxp,imx-gpio";
reg = <0x401c0000 0x4000>;
interrupts = <84 0>, <85 0>;
label = "GPIO_3";
mimxrt1050_evk: Move led and button definitions to dts Moves the led and button definitions for the mimxrt1050_evk board from board.h to dts. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-14 13:52:45 -05:00
gpio-controller;
#gpio-cells = <2>;
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
};
gpio4: gpio@401c4000 {
compatible = "nxp,imx-gpio";
reg = <0x401c4000 0x4000>;
interrupts = <86 0>, <87 0>;
label = "GPIO_4";
mimxrt1050_evk: Move led and button definitions to dts Moves the led and button definitions for the mimxrt1050_evk board from board.h to dts. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-14 13:52:45 -05:00
gpio-controller;
#gpio-cells = <2>;
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
};
gpio5: gpio@400c0000 {
compatible = "nxp,imx-gpio";
reg = <0x400c0000 0x4000>;
interrupts = <88 0>, <89 0>;
label = "GPIO_5";
mimxrt1050_evk: Move led and button definitions to dts Moves the led and button definitions for the mimxrt1050_evk board from board.h to dts. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-05-14 13:52:45 -05:00
gpio-controller;
#gpio-cells = <2>;
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpi2c1: i2c@403f0000 {
dts: Add bindings for imx lpi2c Adds device tree bindings for the imx lpi2c peripheral. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-16 15:03:51 -06:00
compatible = "nxp,imx-lpi2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x403f0000 0x4000>;
interrupts = <28 0>;
clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 6>;
label = "I2C_1";
status = "disabled";
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpi2c2: i2c@403f4000 {
dts: Add bindings for imx lpi2c Adds device tree bindings for the imx lpi2c peripheral. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-16 15:03:51 -06:00
compatible = "nxp,imx-lpi2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x403f4000 0x4000>;
interrupts = <29 0>;
clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 8>;
label = "I2C_2";
status = "disabled";
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpi2c3: i2c@403f8000 {
dts: Add bindings for imx lpi2c Adds device tree bindings for the imx lpi2c peripheral. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-16 15:03:51 -06:00
compatible = "nxp,imx-lpi2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x403f8000 0x4000>;
interrupts = <30 0>;
clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 10>;
label = "I2C_3";
status = "disabled";
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpi2c4: i2c@403fc000 {
dts: Add bindings for imx lpi2c Adds device tree bindings for the imx lpi2c peripheral. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-16 15:03:51 -06:00
compatible = "nxp,imx-lpi2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x403fc000 0x4000>;
interrupts = <31 0>;
clocks = <&ccm IMX_CCM_LPI2C_CLK 0x80 24>;
label = "I2C_4";
status = "disabled";
};
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
iomuxc: iomuxc@401f8000 {
reg = <0x401f8000 0x4000>;
label = "PINMUX_0";
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lcdif: display-controller@402b8000 {
dts: Add bindings for the imx lcd display controller Adds device tree bindings for the imx enhanced LCD interface (eLCDIF) controller. The compatible is reused from linux. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-02 11:20:41 -06:00
compatible = "fsl,imx6sx-lcdif";
reg = <0x402b8000 0x4000>;
interrupts = <42 0>;
label = "ELCDIF_1";
status = "disabled";
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpspi1: spi@40394000 {
dts: Add lpspi yaml bindings and dts nodes Adds yaml bindings and dts nodes for the nxp lpspi peripheral. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-14 16:14:32 -05:00
compatible = "nxp,imx-lpspi";
reg = <0x40394000 0x4000>;
interrupts = <32 3>;
label = "SPI_1";
status = "disabled";
clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 0>;
#address-cells = <1>;
#size-cells = <0>;
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpspi2: spi@40398000 {
dts: Add lpspi yaml bindings and dts nodes Adds yaml bindings and dts nodes for the nxp lpspi peripheral. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-14 16:14:32 -05:00
compatible = "nxp,imx-lpspi";
reg = <0x40398000 0x4000>;
interrupts = <33 3>;
label = "SPI_2";
status = "disabled";
clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 2>;
#address-cells = <1>;
#size-cells = <0>;
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpspi3: spi@4039c000 {
dts: Add lpspi yaml bindings and dts nodes Adds yaml bindings and dts nodes for the nxp lpspi peripheral. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-14 16:14:32 -05:00
compatible = "nxp,imx-lpspi";
reg = <0x4039c000 0x4000>;
interrupts = <34 3>;
label = "SPI_3";
status = "disabled";
clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 4>;
#address-cells = <1>;
#size-cells = <0>;
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpspi4: spi@403a0000 {
dts: Add lpspi yaml bindings and dts nodes Adds yaml bindings and dts nodes for the nxp lpspi peripheral. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-14 16:14:32 -05:00
compatible = "nxp,imx-lpspi";
reg = <0x403a0000 0x4000>;
interrupts = <35 3>;
label = "SPI_4";
status = "disabled";
clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 6>;
#address-cells = <1>;
#size-cells = <0>;
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpuart1: uart@40184000 {
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
compatible = "nxp,kinetis-lpuart";
reg = <0x40184000 0x4000>;
interrupts = <20 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 24>;
label = "UART_1";
status = "disabled";
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpuart2: uart@40188000 {
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
compatible = "nxp,kinetis-lpuart";
reg = <0x40188000 0x4000>;
interrupts = <21 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 28>;
label = "UART_2";
status = "disabled";
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpuart3: uart@4018c000 {
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
compatible = "nxp,kinetis-lpuart";
reg = <0x4018c000 0x4000>;
interrupts = <22 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 12>;
label = "UART_3";
status = "disabled";
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpuart4: uart@40190000 {
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
compatible = "nxp,kinetis-lpuart";
reg = <0x40190000 0x4000>;
interrupts = <23 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x6c 24>;
label = "UART_4";
status = "disabled";
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpuart5: uart@40194000 {
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
compatible = "nxp,kinetis-lpuart";
reg = <0x40194000 0x4000>;
interrupts = <24 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 2>;
label = "UART_5";
status = "disabled";
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpuart6: uart@40198000 {
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
compatible = "nxp,kinetis-lpuart";
reg = <0x40198000 0x4000>;
interrupts = <25 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 6>;
label = "UART_6";
status = "disabled";
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpuart7: uart@4019c000 {
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
compatible = "nxp,kinetis-lpuart";
reg = <0x4019c000 0x4000>;
interrupts = <26 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 26>;
label = "UART_7";
status = "disabled";
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
lpuart8: uart@401a0000 {
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
compatible = "nxp,kinetis-lpuart";
reg = <0x401a0000 0x4000>;
interrupts = <27 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x80 14>;
label = "UART_8";
status = "disabled";
};
drivers: eth_mcux: adding i.mx-rt support Enables Networking hardware on i.MX-RT type drivers. Reuses the same eth_mcux driver used by Kinetis family; initialization sequence refactored to work with this board as well. Unlike Kinetis family, i.MX has a single ENET interrupt and we need to discriminate between interrupts using a status register. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-02 15:51:02 +02:00
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
flexpwm1: flexpwm@403dc000 {
compatible = "nxp,flexpwm";
reg = <0x403dc000 0x4000>;
interrupts = <106 0>;
flexpwm1_pwm0: pwm0 {
compatible = "nxp,imx-pwm";
index = <0>;
label = "FLEXPWM1_PWM0";
interrupts = <102 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
flexpwm1_pwm1: pwm1 {
compatible = "nxp,imx-pwm";
index = <1>;
label = "FLEXPWM1_PWM1";
interrupts = <103 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
flexpwm1_pwm2: pwm2 {
compatible = "nxp,imx-pwm";
index = <2>;
label = "FLEXPWM1_PWM2";
interrupts = <104 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
flexpwm1_pwm3: pwm3 {
compatible = "nxp,imx-pwm";
index = <3>;
label = "FLEXPWM1_PWM3";
interrupts = <105 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
};
flexpwm2: flexpwm@403e0000 {
compatible = "nxp,flexpwm";
reg = <0x403e0000 0x4000>;
interrupts = <141 0>;
flexpwm2_pwm0: pwm0 {
compatible = "nxp,imx-pwm";
index = <0>;
label = "FLEXPWM2_PWM0";
interrupts = <137 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
flexpwm2_pwm1: pwm1 {
compatible = "nxp,imx-pwm";
index = <1>;
label = "FLEXPWM2_PWM1";
interrupts = <138 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
flexpwm2_pwm2: pwm2 {
compatible = "nxp,imx-pwm";
index = <2>;
label = "FLEXPWM2_PWM2";
interrupts = <139 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
flexpwm2_pwm3: pwm3 {
compatible = "nxp,imx-pwm";
index = <3>;
label = "FLEXPWM2_PWM3";
interrupts = <140 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
};
flexpwm3: flexpwm@403e4000 {
compatible = "nxp,flexpwm";
reg = <0x403e4000 0x4000>;
interrupts = <146 0>;
flexpwm3_pwm0: pwm0 {
compatible = "nxp,imx-pwm";
index = <0>;
label = "FLEXPWM3_PWM0";
interrupts = <142 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
flexpwm3_pwm1: pwm1 {
compatible = "nxp,imx-pwm";
index = <1>;
label = "FLEXPWM3_PWM1";
interrupts = <143 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
flexpwm3_pwm2: pwm2 {
compatible = "nxp,imx-pwm";
index = <2>;
label = "FLEXPWM3_PWM2";
interrupts = <144 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
flexpwm3_pwm3: pwm3 {
compatible = "nxp,imx-pwm";
index = <3>;
label = "FLEXPWM3_PWM3";
interrupts = <145 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
};
flexpwm4: flexpwm@403e8000 {
compatible = "nxp,flexpwm";
reg = <0x403e8000 0x4000>;
interrupts = <151 0>;
flexpwm4_pwm0: pwm0 {
compatible = "nxp,imx-pwm";
index = <0>;
label = "FLEXPWM4_PWM0";
interrupts = <147 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
flexpwm4_pwm1: pwm1 {
compatible = "nxp,imx-pwm";
index = <1>;
label = "FLEXPWM4_PWM1";
interrupts = <148 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
flexpwm4_pwm2: pwm2 {
compatible = "nxp,imx-pwm";
index = <2>;
label = "FLEXPWM4_PWM2";
interrupts = <149 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
flexpwm4_pwm3: pwm3 {
compatible = "nxp,imx-pwm";
index = <3>;
label = "FLEXPWM4_PWM3";
interrupts = <150 0>;
dts: pwm: nxp: Fixup bindings and dtsi so they build With the new DT checks the dts bindings for "nxp,flexpwm" and "nxp,imx-pwm" had old conventions that we now treat as build errors. Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-07 08:56:35 -05:00
#pwm-cells = <1>;
arm: nxp: imx-rt: default to PWMs being disabled in dts Mark all the individual PWMs as disabled in dts and enable the one explicitly used on the mimxrt1064_evk.dts in the board dts file. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-15 11:59:15 -05:00
status = "disabled";
dts: arm: nxp: rt: Add PWM nodes i.MX RT10XX processors have four eFlexPWM modules, each containing four 2-channels PWM submodules. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-03-04 19:19:25 +01:00
};
};
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
enet: ethernet@402d8000 {
drivers: eth_mcux: adding i.mx-rt support Enables Networking hardware on i.MX-RT type drivers. Reuses the same eth_mcux driver used by Kinetis family; initialization sequence refactored to work with this board as well. Unlike Kinetis family, i.MX has a single ENET interrupt and we need to discriminate between interrupts using a status register. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-02 15:51:02 +02:00
compatible = "nxp,kinetis-ethernet";
reg = <0x402D8000 0x628>;
interrupts = <114 0>;
dts: nxp: Fix typos: interrupts-names -> interrupt-names Found with a 'git grep s-names' while figuring out some scripts/dts code. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-02-18 19:24:19 +01:00
interrupt-names = "COMMON";
drivers: eth_mcux: adding i.mx-rt support Enables Networking hardware on i.MX-RT type drivers. Reuses the same eth_mcux driver used by Kinetis family; initialization sequence refactored to work with this board as well. Unlike Kinetis family, i.MX has a single ENET interrupt and we need to discriminate between interrupts using a status register. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-02 15:51:02 +02:00
status = "disabled";
label = "ETH_0";
ptp {
compatible = "nxp,kinetis-ptp";
status = "disabled";
interrupts = <115 0>;
dts: nxp: Fix typos: interrupts-names -> interrupt-names Found with a 'git grep s-names' while figuring out some scripts/dts code. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-02-18 19:24:19 +01:00
interrupt-names = "IEEE1588_TMR";
drivers: eth_mcux: adding i.mx-rt support Enables Networking hardware on i.MX-RT type drivers. Reuses the same eth_mcux driver used by Kinetis family; initialization sequence refactored to work with this board as well. Unlike Kinetis family, i.MX has a single ENET interrupt and we need to discriminate between interrupts using a status register. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-02 15:51:02 +02:00
};
};
soc: nxp_imx: Add support for TRNG Add support for the TRNG device contained in the i.MX RT SoCs. It uses the existing MCUX driver, and mostly consists in adding the Kconfig and DTS entries. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2019-01-10 00:56:25 +01:00
dts: arm: nxp: Fix dtc warning from nxp_rt.dtsi We get warnings from dtc when building any of the NXP i.MX-RT boards of the form: mimxrt1020_evk.dts_compiled: Warning (simple_bus_reg): /soc/random@400CC000: simple-bus unit address format error, expected "400cc000" Simple fix to make everything lowercase to have the unit-address and reg match. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-01-16 12:25:49 -06:00
trng: random@400cc000 {
soc: nxp_imx: Add support for TRNG Add support for the TRNG device contained in the i.MX RT SoCs. It uses the existing MCUX driver, and mostly consists in adding the Kconfig and DTS entries. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2019-01-10 00:56:25 +01:00
compatible = "nxp,kinetis-trng";
dts: arm: nxp: Fix dtc warning from nxp_rt.dtsi We get warnings from dtc when building any of the NXP i.MX-RT boards of the form: mimxrt1020_evk.dts_compiled: Warning (simple_bus_reg): /soc/random@400CC000: simple-bus unit address format error, expected "400cc000" Simple fix to make everything lowercase to have the unit-address and reg match. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-01-16 12:25:49 -06:00
reg = <0x400cc000 0x4000>;
dts: Replace status = "ok" with status = "okay" The DT spec. only has "okay" and not "ok". The Linux kernel has around 12k "okay"s and 300 "ok"s. The scripts/dts scripts only check for "disabled", so should be safe re. those at least. The replacement was done with git ls-files | xargs sed -i 's/status\s*=\s*"ok"/status = "okay"/' Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-06-14 19:31:16 +02:00
status = "okay";
soc: nxp_imx: Add support for TRNG Add support for the TRNG device contained in the i.MX RT SoCs. It uses the existing MCUX driver, and mostly consists in adding the Kconfig and DTS entries. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2019-01-10 00:56:25 +01:00
interrupts = <53 0>;
label = "TRNG";
};
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
usb1: usbd@402e0000 {
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
compatible = "nxp,kinetis-usbd";
dts: nxp: nxp_rt: add usbd1 for rt1050 and works as default usb. add usbd1 and use it as the default usb device. Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-27 15:06:31 +08:00
reg = <0x402E0000 0x200>;
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
interrupts = <113 1>;
interrupt-names = "usb_otg";
dts: Add information about system bus frequency to the dts This commit adds a fixed clock node (representing clock driving system bus). The added node is then referenced by peripherals requiring information about driving clock frequency. Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-06-21 14:49:23 +02:00
clocks = <&sysclk>;
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
num-bidir-endpoints = <8>;
maximum-speed = "full-speed";
status = "disabled";
label = "USBD_1";
};
dts: nxp: nxp_rt: add usbd1 for rt1050 and works as default usb. add usbd1 and use it as the default usb device. Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-27 15:06:31 +08:00
dts: arm: nxp: nxp_rt: rename nodelabels to match SoC docs Have nodelabels match the SoC docs so when a nodelabel reference is made in the code its easier to relate to the SoC. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-14 10:03:32 -05:00
usb2: usbd@402e0200 {
dts: nxp: nxp_rt: add usbd1 for rt1050 and works as default usb. add usbd1 and use it as the default usb device. Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-27 15:06:31 +08:00
compatible = "nxp,kinetis-usbd";
reg = <0x402E0200 0x200>;
interrupts = <112 1>;
interrupt-names = "usb_otg";
num-bidir-endpoints = <8>;
maximum-speed = "full-speed";
status = "disabled";
label = "USBD_2";
};
dts/sdhc: support mmc dts and usdhc dts 1) dts/bindings/mmc/mmc.yaml: specifies common mmc. 2) dts/bindings/mmc/nxp,imx-usdhc.yaml: specifies nxp usdhc module which inherits mmc. 3) dts/arm/nxp/nxp_rt.dtsi: usdhc support on RT chip. 4) boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts: usdhc slot support on mimxrt1050_evk board. Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-03 21:07:18 -07:00
usdhc1: usdhc@402c0000 {
compatible = "nxp,imx-usdhc";
reg = <0x402c0000 0x4000>;
status = "disabled";
interrupts = <110 0>;
clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>;
label = "USDHC_1";
};
usdhc2: usdhc@402c4000 {
compatible = "nxp,imx-usdhc";
reg = <0x402c4000 0x4000>;
status = "disabled";
interrupts = <111 0>;
clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>;
label = "USDHC_2";
};
soc: nxp: rt: Add CSI video support Add CSI node to generic nxp rt dtsi. Add corresponding dts binding. Add CSI capability for rt MCUs. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-07-01 14:47:14 +02:00
csi: csi@402bc000 {
compatible = "nxp,imx-csi";
reg = <0x402BC000 0x4000>;
interrupts = <43 1>;
status = "disabled";
label = "CSI";
};
dt-bindings: dts/arm/nxp : add MCUX EDMA Support add MCUX EDMA support for dts binding Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2020-05-15 17:07:26 +08:00
edma0: dma-controller@400e8000 {
#dma-cells = <2>;
compatible = "nxp,mcux-edma";
dma-channels = <32>;
dma-requests = <128>;
nxp,mem2mem;
nxp,a_on;
reg = <0x400E8000 0x4000>,
<0x400EC000 0x4000>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>, <6 0>, <7 0>,
<8 0>, <9 0>, <10 0>, <11 0>,
<12 0>, <13 0>, <14 0>, <15 0>,
<16 0>;
clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
status = "disabled";
label = "EDMA0";
};
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
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