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zephyr/soc/arm/nuvoton_npcx/common/registers.c

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soc: common: npcx: move power.c and registers.c to common folder. This CL moves power policy source file for all npcx series to common folder. It also abstracts the sources for checking register structures to common/registers.c to avoid the duplicated sources in the later npcx series. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-04-27 01:09:05 -07:00
/*
* Copyright (c) 2021 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
soc: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all soc code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 11:11:04 +02:00
#include <zephyr/device.h>
soc: common: npcx: move power.c and registers.c to common folder. This CL moves power policy source file for all npcx series to common folder. It also abstracts the sources for checking register structures to common/registers.c to avoid the duplicated sources in the later npcx series. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-04-27 01:09:05 -07:00
#include <soc.h>
/* CDCG register structure check */
NPCX_REG_SIZE_CHECK(cdcg_reg, 0x116);
NPCX_REG_OFFSET_CHECK(cdcg_reg, HFCBCD, 0x010);
NPCX_REG_OFFSET_CHECK(cdcg_reg, HFCBCD2, 0x014);
NPCX_REG_OFFSET_CHECK(cdcg_reg, LFCGCTL, 0x100);
NPCX_REG_OFFSET_CHECK(cdcg_reg, LFCGCTL2, 0x114);
/* PMC register structure check */
NPCX_REG_SIZE_CHECK(pmc_reg, 0x025);
NPCX_REG_OFFSET_CHECK(pmc_reg, ENIDL_CTL, 0x003);
NPCX_REG_OFFSET_CHECK(pmc_reg, PWDWN_CTL1, 0x008);
NPCX_REG_OFFSET_CHECK(pmc_reg, PWDWN_CTL7, 0x024);
/* SCFG register structure check */
NPCX_REG_SIZE_CHECK(scfg_reg, 0x02f);
NPCX_REG_OFFSET_CHECK(scfg_reg, DEV_CTL4, 0x006);
NPCX_REG_OFFSET_CHECK(scfg_reg, DEVALT0, 0x010);
NPCX_REG_OFFSET_CHECK(scfg_reg, LV_GPIO_CTL0, 0x02a);
/* GLUE register structure check */
NPCX_REG_SIZE_CHECK(glue_reg, 0x028);
NPCX_REG_OFFSET_CHECK(glue_reg, SMB_EEN, 0x003);
NPCX_REG_OFFSET_CHECK(glue_reg, SDPD0, 0x010);
NPCX_REG_OFFSET_CHECK(glue_reg, SMB_SEL, 0x021);
NPCX_REG_OFFSET_CHECK(glue_reg, PSL_CTS, 0x027);
/* UART register structure check */
NPCX_REG_SIZE_CHECK(uart_reg, 0x027);
NPCX_REG_OFFSET_CHECK(uart_reg, UPSR, 0x00e);
NPCX_REG_OFFSET_CHECK(uart_reg, UFTSTS, 0x020);
NPCX_REG_OFFSET_CHECK(uart_reg, UFRCTL, 0x026);
/* GPIO register structure check */
NPCX_REG_SIZE_CHECK(gpio_reg, 0x008);
NPCX_REG_OFFSET_CHECK(gpio_reg, PLOCK_CTL, 0x007);
/* PWM register structure check */
NPCX_REG_SIZE_CHECK(pwm_reg, 0x00e);
NPCX_REG_OFFSET_CHECK(pwm_reg, PWMCTL, 0x004);
NPCX_REG_OFFSET_CHECK(pwm_reg, DCR, 0x006);
NPCX_REG_OFFSET_CHECK(pwm_reg, PWMCTLEX, 0x00c);
/* ADC register structure check */
drivers: adc: npcx: Fix register offset NPCX7/9 has a different ADC register structure. NPCX7 has 3 threshold detectors from offset 0x14 & has 10 input channels. NPCX9 has 6 threshold detectors from offset 0x60 & has 12 input channels. This commit fixes the NPCX ADC register structure. Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
2021-12-13 13:33:50 +08:00
NPCX_REG_SIZE_CHECK(adc_reg, 0x028);
NPCX_REG_OFFSET_CHECK(adc_reg, THRCTS, 0x01a);
soc: common: npcx: move power.c and registers.c to common folder. This CL moves power policy source file for all npcx series to common folder. It also abstracts the sources for checking register structures to common/registers.c to avoid the duplicated sources in the later npcx series. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-04-27 01:09:05 -07:00
NPCX_REG_OFFSET_CHECK(adc_reg, ADCCNF2, 0x020);
drivers: adc: npcx: Fix register offset NPCX7/9 has a different ADC register structure. NPCX7 has 3 threshold detectors from offset 0x14 & has 10 input channels. NPCX9 has 6 threshold detectors from offset 0x60 & has 12 input channels. This commit fixes the NPCX ADC register structure. Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
2021-12-13 13:33:50 +08:00
NPCX_REG_OFFSET_CHECK(adc_reg, MEAST, 0x026);
soc: common: npcx: move power.c and registers.c to common folder. This CL moves power policy source file for all npcx series to common folder. It also abstracts the sources for checking register structures to common/registers.c to avoid the duplicated sources in the later npcx series. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-04-27 01:09:05 -07:00
/* TWD register structure check */
NPCX_REG_SIZE_CHECK(twd_reg, 0x012);
NPCX_REG_OFFSET_CHECK(twd_reg, T0CSR, 0x006);
NPCX_REG_OFFSET_CHECK(twd_reg, TWMWD, 0x00e);
NPCX_REG_OFFSET_CHECK(twd_reg, WDCP, 0x010);
/* ESPI register structure check */
NPCX_REG_SIZE_CHECK(espi_reg, 0x500);
NPCX_REG_OFFSET_CHECK(espi_reg, FLASHCFG, 0x034);
driver: eSPI: npcx: workaround the errata rev1_2, No.3.10 Enabling an eSPI channel (r.g. Peripheral Channel, Virtual Wire Channel, etc.) during an eSPI transaction might (with low probability) cause the eSPI_SIF module to transition to a wrong state and therefore response with FATAL_ERROR on an incoming transaction. This CL workarounds this issue by clearing the bit 4 of NPCX eSPI specific register#2. Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-04-27 16:42:37 +08:00
NPCX_REG_OFFSET_CHECK(espi_reg, NPCX_ONLY_ESPI_REG1, 0x0f0);
soc: common: npcx: move power.c and registers.c to common folder. This CL moves power policy source file for all npcx series to common folder. It also abstracts the sources for checking register structures to common/registers.c to avoid the duplicated sources in the later npcx series. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2021-04-27 01:09:05 -07:00
NPCX_REG_OFFSET_CHECK(espi_reg, VWEVMS, 0x140);
NPCX_REG_OFFSET_CHECK(espi_reg, VWCTL, 0x2fc);
NPCX_REG_OFFSET_CHECK(espi_reg, OOBTXBUF, 0x380);
NPCX_REG_OFFSET_CHECK(espi_reg, OOBCTL_DIRECT, 0x3fc);
NPCX_REG_OFFSET_CHECK(espi_reg, FLASHTXBUF, 0x480);
NPCX_REG_OFFSET_CHECK(espi_reg, FLASHCTL_DIRECT, 0x4fc);
/* MSWC register structure check */
NPCX_REG_SIZE_CHECK(mswc_reg, 0x030);
NPCX_REG_OFFSET_CHECK(mswc_reg, HCBAL, 0x008);
NPCX_REG_OFFSET_CHECK(mswc_reg, HCBAH, 0x00a);
NPCX_REG_OFFSET_CHECK(mswc_reg, SRID_CR, 0x01c);
NPCX_REG_OFFSET_CHECK(mswc_reg, SID_CR, 0x020);
NPCX_REG_OFFSET_CHECK(mswc_reg, VW_SLPST1, 0x02e);
/* SHM register structure check */
NPCX_REG_SIZE_CHECK(shm_reg, 0x050);
NPCX_REG_OFFSET_CHECK(shm_reg, IMA_WIN_SIZE, 0x005);
NPCX_REG_OFFSET_CHECK(shm_reg, WIN_SIZE, 0x007);
NPCX_REG_OFFSET_CHECK(shm_reg, IMA_SEM, 0x00b);
NPCX_REG_OFFSET_CHECK(shm_reg, SHCFG, 0x00e);
NPCX_REG_OFFSET_CHECK(shm_reg, WIN1_WR_PROT, 0x010);
NPCX_REG_OFFSET_CHECK(shm_reg, IMA_WR_PROT, 0x016);
NPCX_REG_OFFSET_CHECK(shm_reg, WIN_BASE1, 0x020);
NPCX_REG_OFFSET_CHECK(shm_reg, WIN_BASE2, 0x024);
NPCX_REG_OFFSET_CHECK(shm_reg, RST_CFG, 0x03a);
NPCX_REG_OFFSET_CHECK(shm_reg, DP80BUF, 0x040);
NPCX_REG_OFFSET_CHECK(shm_reg, DP80CTL, 0x044);
NPCX_REG_OFFSET_CHECK(shm_reg, HOFS_STS, 0x048);
NPCX_REG_OFFSET_CHECK(shm_reg, COFS1, 0x04c);
/* KBC register structure check */
NPCX_REG_SIZE_CHECK(kbc_reg, 0x00c);
NPCX_REG_OFFSET_CHECK(kbc_reg, HIKMDI, 0x00a);
NPCX_REG_OFFSET_CHECK(kbc_reg, SHIKMDI, 0x00b);
/* PMCH register structure check */
NPCX_REG_SIZE_CHECK(pmch_reg, 0x012);
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMDO, 0x002);
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMDOC, 0x006);
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMDOM, 0x008);
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMDIC, 0x00a);
NPCX_REG_OFFSET_CHECK(pmch_reg, HIPMIE, 0x010);
/* C2H register structure check */
NPCX_REG_SIZE_CHECK(c2h_reg, 0x00c);
NPCX_REG_OFFSET_CHECK(c2h_reg, LKSIOHA, 0x004);
NPCX_REG_OFFSET_CHECK(c2h_reg, CRSMAE, 0x008);
NPCX_REG_OFFSET_CHECK(c2h_reg, SIBCTRL, 0x00a);
/* SMB register structure check */
NPCX_REG_SIZE_CHECK(smb_reg, 0x020);
NPCX_REG_OFFSET_CHECK(smb_reg, SMBCTL1, 0x006);
NPCX_REG_OFFSET_CHECK(smb_reg, SMBT_OUT, 0x00f);
NPCX_REG_OFFSET_CHECK(smb_reg, SMBADDR6, 0x016);
NPCX_REG_OFFSET_CHECK(smb_reg, SMBSCLHT, 0x01e);
NPCX_REG_SIZE_CHECK(smb_fifo_reg, 0x020);
NPCX_REG_OFFSET_CHECK(smb_fifo_reg, SMBT_OUT, 0x00f);
NPCX_REG_OFFSET_CHECK(smb_fifo_reg, SMBCST2, 0x018);
NPCX_REG_OFFSET_CHECK(smb_fifo_reg, SMBTXF_STS, 0x01a);
NPCX_REG_OFFSET_CHECK(smb_fifo_reg, SMBRXF_CTL, 0x01e);
/* ITIM register structure check */
NPCX_REG_SIZE_CHECK(itim32_reg, 0x00c);
NPCX_REG_OFFSET_CHECK(itim32_reg, ITPRE32, 0x001);
NPCX_REG_OFFSET_CHECK(itim32_reg, ITCTS32, 0x004);
NPCX_REG_OFFSET_CHECK(itim32_reg, ITCNT32, 0x008);
NPCX_REG_SIZE_CHECK(itim64_reg, 0x010);
NPCX_REG_OFFSET_CHECK(itim64_reg, ITPRE64, 0x001);
NPCX_REG_OFFSET_CHECK(itim64_reg, ITCTS64, 0x004);
NPCX_REG_OFFSET_CHECK(itim64_reg, ITCNT64L, 0x008);
NPCX_REG_OFFSET_CHECK(itim64_reg, ITCNT64H, 0x00c);
/* TACH register structure check */
NPCX_REG_SIZE_CHECK(tach_reg, 0x01e);
NPCX_REG_OFFSET_CHECK(tach_reg, TPRSC, 0x008);
NPCX_REG_OFFSET_CHECK(tach_reg, TECLR, 0x010);
NPCX_REG_OFFSET_CHECK(tach_reg, TCPA, 0x014);
NPCX_REG_OFFSET_CHECK(tach_reg, TCPCFG, 0x018);
NPCX_REG_OFFSET_CHECK(tach_reg, TCFG, 0x01c);
/* Debug Interface register structure check */
NPCX_REG_SIZE_CHECK(dbg_reg, 0x06);
NPCX_REG_OFFSET_CHECK(dbg_reg, DBGCTRL, 0x000);
NPCX_REG_OFFSET_CHECK(dbg_reg, DBGFRZEN2, 0x003);
NPCX_REG_OFFSET_CHECK(dbg_reg, DBGFRZEN4, 0x005);
driver: PS/2: npcx: add driver support for Nuvoton npcx family The PS/2 module in npcx provides a hardware accelerator mechanism including an 8-bit shift register, a state machine, and control logic that handle both the incoming and outgoing data. The hardware accelerator mechanism is shared by 4 PS/2 channels. To support it, this CL separates the PS/2 driver into channel and controller drivers. The controller driver is in charge of the PS/2 transaction. The channel driver is in charge of the connection between the Zehpyr PS/2 API interface and controller driver. Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2021-06-11 15:33:56 +08:00
/* PS/2 Interface register structure check */
NPCX_REG_SIZE_CHECK(ps2_reg, 0x00c);
NPCX_REG_OFFSET_CHECK(ps2_reg, PSDAT, 0x000);
NPCX_REG_OFFSET_CHECK(ps2_reg, PSTAT, 0x002);
NPCX_REG_OFFSET_CHECK(ps2_reg, PSCON, 0x004);
NPCX_REG_OFFSET_CHECK(ps2_reg, PSOSIG, 0x006);
NPCX_REG_OFFSET_CHECK(ps2_reg, PSISIG, 0x008);
NPCX_REG_OFFSET_CHECK(ps2_reg, PSIEN, 0x00a);
drivers: spi: npcx: add SPI support to access the SPI flash The FIU/UMA module in the NPCX chip provides an dedicated SPI interface to access the SPI flash. This commit adds the driver support for it. With this commit, the application can call the flash APIs (via spi_nor.c) to access the internal flash of NPCX EC chips. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I32bbf09f6e014b728ff8e4692e48151ae759e188
2021-10-13 14:17:02 +08:00
/* FIU register structure check */
NPCX_REG_SIZE_CHECK(fiu_reg, 0x034);
NPCX_REG_OFFSET_CHECK(fiu_reg, BURST_CFG, 0x001);
NPCX_REG_OFFSET_CHECK(fiu_reg, SPI_FL_CFG, 0x014);
NPCX_REG_OFFSET_CHECK(fiu_reg, UMA_CTS, 0x01e);
NPCX_REG_OFFSET_CHECK(fiu_reg, CRCCON, 0x026);
NPCX_REG_OFFSET_CHECK(fiu_reg, FIU_RD_CMD, 0x030);
NPCX_REG_OFFSET_CHECK(fiu_reg, FIU_EXT_CFG, 0x033);
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