zephyr/soc/riscv/renode_virt/Kconfig.soc

# Copyright (c) 2023 Meta
# SPDX-License-Identifier: Apache-2.0

config SOC_RISCV32_VIRTUAL_RENODE
	bool "Renode RISCV32 Virtual system implementation"
	select RISCV
	select RISCV_PRIVILEGED
	select ATOMIC_OPERATIONS_BUILTIN
	select INCLUDE_RESET_VECTOR
	select RISCV_ISA_RV32I
	select RISCV_ISA_EXT_M
	select RISCV_ISA_EXT_A
	select RISCV_ISA_EXT_C
	select RISCV_ISA_EXT_ZICSR
	select RISCV_ISA_EXT_ZIFENCEI
	select RISCV_HAS_PLIC
soc: riscv: add support for Renode Virt RISCV32 SoC Add a beef-ed up version of Renode's `riscv_virt` SoC Signed-off-by: Yong Cong Sin <ycsin@meta.com> 2023-12-23 17:35:24 +08:00			`# Copyright (c) 2023 Meta`
			`# SPDX-License-Identifier: Apache-2.0`

			`config SOC_RISCV32_VIRTUAL_RENODE`
			`bool "Renode RISCV32 Virtual system implementation"`
soc: riscv: renove_virt: reorganize SoC folder Move out from riscv-privileged, and convert to a standalone SoC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com> 2024-01-08 14:13:06 +01:00			`select RISCV`
			`select RISCV_PRIVILEGED`
soc: riscv: add support for Renode Virt RISCV32 SoC Add a beef-ed up version of Renode's `riscv_virt` SoC Signed-off-by: Yong Cong Sin <ycsin@meta.com> 2023-12-23 17:35:24 +08:00			`select ATOMIC_OPERATIONS_BUILTIN`
			`select INCLUDE_RESET_VECTOR`
			`select RISCV_ISA_RV32I`
			`select RISCV_ISA_EXT_M`
			`select RISCV_ISA_EXT_A`
			`select RISCV_ISA_EXT_C`
			`select RISCV_ISA_EXT_ZICSR`
			`select RISCV_ISA_EXT_ZIFENCEI`
soc: riscv: make RISCV_HAS_(C\|P)LIC promptless These options are meant to be selected by SoC series supporting (C\|P)LIC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com> 2024-01-16 15:55:41 +01:00			`select RISCV_HAS_PLIC`