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zephyr/soc/espressif/esp32/Kconfig.defconfig

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soc: xtensa,riscv: esp32xx: refactor folder structure Refactor the ESP32 target SOCs together with all related boards. Most braking changes includes: - changing the CONFIG_SOC_ESP32* to refer to the actual soc line (esp32,esp32s2,esp32s3,esp32c3) - replacing CONFIG_SOC with the CONFIG_SOC_SERIES - creating CONFIG_SOC_FAMILY_ESP32 to embrace all the ESP32 across all used architectures - introducing CONFIG_SOC_PART_NUMBER_* to provide a SOC model config - introducing the 'common' folder to hide all commonly used configs and files. - updating west.yml to reflect previous changes in hal Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-20 18:24:09 +02:00
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
arch: xtensa: Add ESP32 SoC Due to the configurable nature of the Xtensa platform, the generic name of "LX6" cannot be used to describe an SoC as far as Zephyr goes. So ESP32 is defined both as a SoC and as a board. This is based on work by Rajavardhan Gundi. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-05-03 14:28:12 -07:00
# SPDX-License-Identifier: Apache-2.0
soc: xtensa,riscv: esp32xx: refactor folder structure Refactor the ESP32 target SOCs together with all related boards. Most braking changes includes: - changing the CONFIG_SOC_ESP32* to refer to the actual soc line (esp32,esp32s2,esp32s3,esp32c3) - replacing CONFIG_SOC with the CONFIG_SOC_SERIES - creating CONFIG_SOC_FAMILY_ESP32 to embrace all the ESP32 across all used architectures - introducing CONFIG_SOC_PART_NUMBER_* to provide a SOC model config - introducing the 'common' folder to hide all commonly used configs and files. - updating west.yml to reflect previous changes in hal Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-20 18:24:09 +02:00
if SOC_SERIES_ESP32
arch: xtensa: Add ESP32 SoC Due to the configurable nature of the Xtensa platform, the generic name of "LX6" cannot be used to describe an SoC as far as Zephyr goes. So ESP32 is defined both as a SoC and as a board. This is based on work by Rajavardhan Gundi. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-05-03 14:28:12 -07:00
soc: xtensa,riscv: esp32xx: refactor folder structure Refactor the ESP32 target SOCs together with all related boards. Most braking changes includes: - changing the CONFIG_SOC_ESP32* to refer to the actual soc line (esp32,esp32s2,esp32s3,esp32c3) - replacing CONFIG_SOC with the CONFIG_SOC_SERIES - creating CONFIG_SOC_FAMILY_ESP32 to embrace all the ESP32 across all used architectures - introducing CONFIG_SOC_PART_NUMBER_* to provide a SOC model config - introducing the 'common' folder to hide all commonly used configs and files. - updating west.yml to reflect previous changes in hal Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-20 18:24:09 +02:00
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
default n
soc: esp32: add support to mcuboot build Select configuration when mcuboot is enabled. At this moment, only UNSIGNED image is supported as per Espressif's mcuboot porting. This also updates esp32 runner to use proper bin_file name and updates default bootloader check. Move CMakeLists.txt content from board to soc directory as this support is for esp32 architecture and not board specific. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-11-27 16:32:00 -03:00
soc: xtensa,riscv: esp32xx: refactor folder structure Refactor the ESP32 target SOCs together with all related boards. Most braking changes includes: - changing the CONFIG_SOC_ESP32* to refer to the actual soc line (esp32,esp32s2,esp32s3,esp32c3) - replacing CONFIG_SOC with the CONFIG_SOC_SERIES - creating CONFIG_SOC_FAMILY_ESP32 to embrace all the ESP32 across all used architectures - introducing CONFIG_SOC_PART_NUMBER_* to provide a SOC model config - introducing the 'common' folder to hide all commonly used configs and files. - updating west.yml to reflect previous changes in hal Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-20 18:24:09 +02:00
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
soc: esp32: add support to mcuboot build Select configuration when mcuboot is enabled. At this moment, only UNSIGNED image is supported as per Espressif's mcuboot porting. This also updates esp32 runner to use proper bin_file name and updates default bootloader check. Move CMakeLists.txt content from board to soc directory as this support is for esp32 architecture and not board specific. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-11-27 16:32:00 -03:00
soc: xtensa,riscv: esp32xx: refactor folder structure Refactor the ESP32 target SOCs together with all related boards. Most braking changes includes: - changing the CONFIG_SOC_ESP32* to refer to the actual soc line (esp32,esp32s2,esp32s3,esp32c3) - replacing CONFIG_SOC with the CONFIG_SOC_SERIES - creating CONFIG_SOC_FAMILY_ESP32 to embrace all the ESP32 across all used architectures - introducing CONFIG_SOC_PART_NUMBER_* to provide a SOC model config - introducing the 'common' folder to hide all commonly used configs and files. - updating west.yml to reflect previous changes in hal Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-20 18:24:09 +02:00
config XTENSA_CCOUNT_HZ
default SYS_CLOCK_HW_CYCLES_PER_SEC
soc: esp32: add support to mcuboot build Select configuration when mcuboot is enabled. At this moment, only UNSIGNED image is supported as per Espressif's mcuboot porting. This also updates esp32 runner to use proper bin_file name and updates default bootloader check. Move CMakeLists.txt content from board to soc directory as this support is for esp32 architecture and not board specific. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-11-27 16:32:00 -03:00
soc: xtensa,riscv: esp32xx: refactor folder structure Refactor the ESP32 target SOCs together with all related boards. Most braking changes includes: - changing the CONFIG_SOC_ESP32* to refer to the actual soc line (esp32,esp32s2,esp32s3,esp32c3) - replacing CONFIG_SOC with the CONFIG_SOC_SERIES - creating CONFIG_SOC_FAMILY_ESP32 to embrace all the ESP32 across all used architectures - introducing CONFIG_SOC_PART_NUMBER_* to provide a SOC model config - introducing the 'common' folder to hide all commonly used configs and files. - updating west.yml to reflect previous changes in hal Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-20 18:24:09 +02:00
config ESPTOOLPY_FLASHFREQ_80M
default y
arch: xtensa: Add ESP32 SoC Due to the configurable nature of the Xtensa platform, the generic name of "LX6" cannot be used to describe an SoC as far as Zephyr goes. So ESP32 is defined both as a SoC and as a board. This is based on work by Rajavardhan Gundi. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-05-03 14:28:12 -07:00
soc: xtensa,riscv: esp32xx: refactor folder structure Refactor the ESP32 target SOCs together with all related boards. Most braking changes includes: - changing the CONFIG_SOC_ESP32* to refer to the actual soc line (esp32,esp32s2,esp32s3,esp32c3) - replacing CONFIG_SOC with the CONFIG_SOC_SERIES - creating CONFIG_SOC_FAMILY_ESP32 to embrace all the ESP32 across all used architectures - introducing CONFIG_SOC_PART_NUMBER_* to provide a SOC model config - introducing the 'common' folder to hide all commonly used configs and files. - updating west.yml to reflect previous changes in hal Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-20 18:24:09 +02:00
config FLASH_SIZE
default $(dt_node_reg_size_int,/soc/flash-controller@3ff42000/flash@0,0)
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,/soc/flash-controller@3ff42000/flash@0)
soc: esp32: add toolchain name Add ESP32 and ESP32S2 toolchain name that is addressed when integrated with zephyr-sdk. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-03-02 17:44:08 -03:00
soc: xtensa: esp32: reenable SMP for esp32 By enabling SMP option plus the APPCPU, also completes the SMP port by adding the esp32 specific arch_sched_ipi() function Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-11-10 14:06:16 -03:00
if SMP
config SCHED_IPI_SUPPORTED
default y
config SCHED_CPU_MASK
default y
smp: Kconfig: Move to using MP_MAX_NUM_CPUS Continue to phase out MP_NUM_CPUS, change Kconfig to be MP_MAX_NUM_CPUS and make MP_MAX_NUM_CPUS the main Kconfig symbol. Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2022-10-19 17:51:30 -05:00
config MP_MAX_NUM_CPUS
soc: xtensa: esp32: reenable SMP for esp32 By enabling SMP option plus the APPCPU, also completes the SMP port by adding the esp32 specific arch_sched_ipi() function Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-11-10 14:06:16 -03:00
default 2
soc: xtensa,riscv: esp32xx: refactor folder structure Refactor the ESP32 target SOCs together with all related boards. Most braking changes includes: - changing the CONFIG_SOC_ESP32* to refer to the actual soc line (esp32,esp32s2,esp32s3,esp32c3) - replacing CONFIG_SOC with the CONFIG_SOC_SERIES - creating CONFIG_SOC_FAMILY_ESP32 to embrace all the ESP32 across all used architectures - introducing CONFIG_SOC_PART_NUMBER_* to provide a SOC model config - introducing the 'common' folder to hide all commonly used configs and files. - updating west.yml to reflect previous changes in hal Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-20 18:24:09 +02:00
endif # SMP config
soc: esp32: add CCOUNT xtensa rate default value Xtensa's ESP32 misses this base CCOUNT value, which causes wrong arch_timing_freq_get() value reference. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2022-12-20 08:38:08 -03:00
soc: esp32: add support for GDB stub This adds the SoC specific bits to enable GDB stub, mainly the description for the register file, and memory regions. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-10-26 13:00:16 -07:00
if GDBSTUB
# ESP32 GDB expects 420 bytes G-packet.
# So double for hexadecimal digits.
config GDBSTUB_BUF_SZ
default 840 if GDBSTUB
soc: xtensa,riscv: esp32xx: refactor folder structure Refactor the ESP32 target SOCs together with all related boards. Most braking changes includes: - changing the CONFIG_SOC_ESP32* to refer to the actual soc line (esp32,esp32s2,esp32s3,esp32c3) - replacing CONFIG_SOC with the CONFIG_SOC_SERIES - creating CONFIG_SOC_FAMILY_ESP32 to embrace all the ESP32 across all used architectures - introducing CONFIG_SOC_PART_NUMBER_* to provide a SOC model config - introducing the 'common' folder to hide all commonly used configs and files. - updating west.yml to reflect previous changes in hal Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-20 18:24:09 +02:00
endif # GDBSTUB config
soc: esp32: add support for GDB stub This adds the SoC specific bits to enable GDB stub, mainly the description for the register file, and memory regions. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-10-26 13:00:16 -07:00
soc: xtensa,riscv: esp32xx: refactor folder structure Refactor the ESP32 target SOCs together with all related boards. Most braking changes includes: - changing the CONFIG_SOC_ESP32* to refer to the actual soc line (esp32,esp32s2,esp32s3,esp32c3) - replacing CONFIG_SOC with the CONFIG_SOC_SERIES - creating CONFIG_SOC_FAMILY_ESP32 to embrace all the ESP32 across all used architectures - introducing CONFIG_SOC_PART_NUMBER_* to provide a SOC model config - introducing the 'common' folder to hide all commonly used configs and files. - updating west.yml to reflect previous changes in hal Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-20 18:24:09 +02:00
endif # SOC_SERIES_ESP32 config
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