440 lines
13 KiB
C
440 lines
13 KiB
C
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/*
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* Copyright (c) 2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT adi_max32_i2c
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#include <errno.h>
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/drivers/i2c/rtio.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
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#include <zephyr/irq.h>
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#include <wrap_max32_i2c.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(max32_i2c);
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#define ADI_MAX32_I2C_INT_FL0_MASK 0x00FFFFFF
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#define ADI_MAX32_I2C_INT_FL1_MASK 0x7
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#define ADI_MAX32_I2C_STATUS_MASTER_BUSY BIT(5)
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#define I2C_RECOVER_MAX_RETRIES 3
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#define I2C_STANDAR_BITRATE_CLKHI 0x12b
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static int complete_flag;
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/* Driver config */
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struct max32_i2c_config {
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mxc_i2c_regs_t *regs;
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const struct pinctrl_dev_config *pctrl;
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const struct device *clock;
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struct max32_perclk perclk;
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uint32_t bitrate;
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#if defined(CONFIG_I2C_MAX32_INTERRUPT)
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uint8_t irqn;
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void (*irq_config_func)(const struct device *dev);
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#endif
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};
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struct max32_i2c_data {
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mxc_i2c_req_t req;
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const struct device *dev;
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uint8_t target_mode;
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uint8_t flags;
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struct i2c_rtio *ctx;
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uint32_t readb;
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uint32_t written;
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uint8_t second_msg_flag;
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#if defined(CONFIG_I2C_MAX32_INTERRUPT)
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int err;
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#endif
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};
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static int max32_configure(const struct device *dev,
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uint32_t dev_cfg)
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{
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struct i2c_rtio *const ctx = ((struct max32_i2c_data *)
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dev->data)->ctx;
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return i2c_rtio_configure(ctx, dev_cfg);
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}
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static int max32_do_configure(const struct device *dev, uint32_t dev_cfg)
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{
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int ret = 0;
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const struct max32_i2c_config *const cfg = dev->config;
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mxc_i2c_regs_t *i2c = cfg->regs;
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switch (I2C_SPEED_GET(dev_cfg)) {
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case I2C_SPEED_STANDARD: /** I2C Standard Speed: 100 kHz */
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ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_STD_MODE);
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break;
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case I2C_SPEED_FAST: /** I2C Fast Speed: 400 kHz */
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ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FAST_SPEED);
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break;
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#if defined(MXC_I2C_FASTPLUS_SPEED)
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case I2C_SPEED_FAST_PLUS: /** I2C Fast Plus Speed: 1 MHz */
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ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FASTPLUS_SPEED);
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break;
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#endif
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#if defined(MXC_I2C_HIGH_SPEED)
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case I2C_SPEED_HIGH: /** I2C High Speed: 3.4 MHz */
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ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_HIGH_SPEED);
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break;
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#endif
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default:
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/* Speed not supported */
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return -ENOTSUP;
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}
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return ret;
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}
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static void max32_complete(const struct device *dev, int status);
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static int max32_msg_start(const struct device *dev, uint8_t flags,
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uint8_t *buf, size_t buf_len, uint16_t i2c_addr)
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{
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int ret = 0;
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const struct max32_i2c_config *const cfg = dev->config;
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struct max32_i2c_data *data = dev->data;
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mxc_i2c_regs_t *i2c = cfg->regs;
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mxc_i2c_req_t *req = &data->req;
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uint8_t target_rw;
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req->i2c = i2c;
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req->addr = i2c_addr;
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if (data->second_msg_flag == 0) {
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MXC_I2C_ClearRXFIFO(i2c);
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MXC_I2C_ClearTXFIFO(i2c);
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MXC_I2C_SetRXThreshold(i2c, 1);
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/* First message should always begin with a START condition */
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flags |= I2C_MSG_RESTART;
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}
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if (flags & I2C_MSG_READ) {
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req->rx_buf = (unsigned char *)buf;
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req->rx_len = buf_len;
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req->tx_buf = NULL;
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req->tx_len = 0;
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target_rw = (i2c_addr << 1) | 0x1;
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} else {
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req->tx_buf = (unsigned char *)buf;
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req->tx_len = buf_len;
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req->rx_buf = NULL;
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req->rx_len = 0;
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target_rw = (i2c_addr << 1) & ~0x1;
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}
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data->flags = flags;
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data->readb = 0;
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data->written = 0;
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data->err = 0;
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MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
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MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ERR, 0);
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Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len);
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if ((data->flags & I2C_MSG_RESTART)) {
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MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
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MXC_I2C_Start(i2c);
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Wrap_MXC_I2C_WaitForRestart(i2c);
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MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
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} else {
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if (req->tx_len) {
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data->written = MXC_I2C_WriteTXFIFO(i2c, req->tx_buf, 1);
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MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
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} else {
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MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_RX_THD, 0);
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}
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}
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if (data->err) {
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MXC_I2C_Stop(i2c);
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ret = data->err;
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}
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return ret;
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}
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static int max32_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
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uint16_t target_address)
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{
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struct i2c_rtio *const ctx = ((struct max32_i2c_data *)
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dev->data)->ctx;
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((struct max32_i2c_data *)dev->data)->second_msg_flag = 0;
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return i2c_rtio_transfer(ctx, msgs, num_msgs, target_address);
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}
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static void i2c_max32_isr_controller(const struct device *dev, mxc_i2c_regs_t *i2c)
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{
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struct max32_i2c_data *data = dev->data;
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mxc_i2c_req_t *req = &data->req;
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uint32_t written, readb;
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uint32_t txfifolevel;
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uint32_t int_fl0, int_fl1;
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uint32_t int_en0, int_en1;
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written = data->written;
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readb = data->readb;
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Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1);
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MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
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MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
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txfifolevel = Wrap_MXC_I2C_GetTxFIFOLevel(i2c);
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if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
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data->err = -EIO;
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Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
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return;
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}
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if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_ACK) {
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MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
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if (written < req->tx_len) {
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MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
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} else if (readb < req->rx_len) {
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MXC_I2C_EnableInt(
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i2c, ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE, 0);
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}
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}
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if (req->tx_len &&
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(int_fl0 & (ADI_MAX32_I2C_INT_FL0_TX_THD | ADI_MAX32_I2C_INT_FL0_DONE))) {
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if (written < req->tx_len) {
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written += MXC_I2C_WriteTXFIFO(i2c, &req->tx_buf[written],
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req->tx_len - written);
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} else {
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if (!(int_en0 & ADI_MAX32_I2C_INT_EN0_DONE)) {
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/* We are done, stop sending more data */
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MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
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if (data->flags & I2C_MSG_STOP) {
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MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
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/* Done flag is not set if stop/restart is not set */
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Wrap_MXC_I2C_Stop(i2c);
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} else {
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complete_flag++;
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}
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}
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if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE)) {
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MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
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complete_flag++;
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}
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}
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} else if ((int_fl0 & (ADI_MAX32_I2C_INT_FL0_RX_THD | ADI_MAX32_I2C_INT_FL0_DONE))) {
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readb += MXC_I2C_ReadRXFIFO(i2c, &req->rx_buf[readb], req->rx_len - readb);
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if (readb == req->rx_len) {
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MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_RX_THD, 0);
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if (data->flags & I2C_MSG_STOP) {
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MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
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Wrap_MXC_I2C_Stop(i2c);
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complete_flag++;
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} else {
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if (int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE) {
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MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
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}
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}
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} else if ((int_en0 & ADI_MAX32_I2C_INT_EN0_DONE) &&
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(int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE)) {
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MXC_I2C_DisableInt(
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i2c, (ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE),
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0);
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Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len - readb);
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MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
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i2c->fifo = (req->addr << 1) | 0x1;
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Wrap_MXC_I2C_Restart(i2c);
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}
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}
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data->written = written;
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data->readb = readb;
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if (complete_flag == 1) {
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max32_complete(dev, 0);
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complete_flag = 0;
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}
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}
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static bool max32_start(const struct device *dev)
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{
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struct max32_i2c_data *data = dev->data;
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struct i2c_rtio *ctx = data->ctx;
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struct rtio_sqe *sqe = &ctx->txn_curr->sqe;
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struct i2c_dt_spec *dt_spec = sqe->iodev->data;
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int res = 0;
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switch (sqe->op) {
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case RTIO_OP_RX:
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return max32_msg_start(dev, I2C_MSG_READ | sqe->iodev_flags,
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sqe->rx.buf, sqe->rx.buf_len, dt_spec->addr);
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case RTIO_OP_TINY_TX:
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data->second_msg_flag = 0;
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return max32_msg_start(dev, I2C_MSG_WRITE | sqe->iodev_flags,
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(uint8_t *)sqe->tiny_tx.buf, sqe->tiny_tx.buf_len,
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dt_spec->addr);
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case RTIO_OP_TX:
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return max32_msg_start(dev, I2C_MSG_WRITE | sqe->iodev_flags,
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(uint8_t *)sqe->tx.buf, sqe->tx.buf_len,
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dt_spec->addr);
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case RTIO_OP_I2C_CONFIGURE:
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res = max32_do_configure(dev, sqe->i2c_config);
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return i2c_rtio_complete(data->ctx, res);
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default:
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LOG_ERR("Invalid op code %d for submission %p\n", sqe->op, (void *)sqe);
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return i2c_rtio_complete(data->ctx, -EINVAL);
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}
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}
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static void max32_complete(const struct device *dev, int status)
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{
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struct max32_i2c_data *data = dev->data;
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struct i2c_rtio *const ctx = data->ctx;
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const struct max32_i2c_config *const cfg = dev->config;
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int ret = 0;
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if (cfg->regs->clkhi == I2C_STANDAR_BITRATE_CLKHI) {
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/* When I2C is configured in Standard Bitrate 100KHz
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* Hardware completes first read sample transaction
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* and gets stuck in idle instead of starting the
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* next transaction, if given k_busy_wait for
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* 20 us ~= 2 additional I2C cycles sample read
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* won't have any issues but all other transactions
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* (like setup of sensor) will have this unnecessary
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* delay. This doesn't happen when using Fast
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* Bitrate 400Hz.
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*/
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LOG_ERR("For Standard speed HW needs more time to run");
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return;
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}
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if (i2c_rtio_complete(ctx, ret)) {
|
||
|
|
data->second_msg_flag = 1;
|
||
|
|
max32_start(dev);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void max32_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
|
||
|
|
{
|
||
|
|
struct max32_i2c_data *data = dev->data;
|
||
|
|
struct i2c_rtio *const ctx = data->ctx;
|
||
|
|
|
||
|
|
if (i2c_rtio_submit(ctx, iodev_sqe)) {
|
||
|
|
max32_start(dev);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
static void i2c_max32_isr(const struct device *dev)
|
||
|
|
{
|
||
|
|
const struct max32_i2c_config *cfg = dev->config;
|
||
|
|
struct max32_i2c_data *data = dev->data;
|
||
|
|
mxc_i2c_regs_t *i2c = cfg->regs;
|
||
|
|
|
||
|
|
if (data->target_mode == 0) {
|
||
|
|
i2c_max32_isr_controller(dev, i2c);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static int i2c_max32_init(const struct device *dev)
|
||
|
|
{
|
||
|
|
const struct max32_i2c_config *const cfg = dev->config;
|
||
|
|
struct max32_i2c_data *data = dev->data;
|
||
|
|
mxc_i2c_regs_t *i2c = cfg->regs;
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
if (!device_is_ready(cfg->clock)) {
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
|
||
|
|
MXC_I2C_Shutdown(i2c); /* Clear everything out */
|
||
|
|
|
||
|
|
ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk);
|
||
|
|
if (ret) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = pinctrl_apply_state(cfg->pctrl, PINCTRL_STATE_DEFAULT);
|
||
|
|
if (ret) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = MXC_I2C_Init(i2c, 1, 0); /* Configure as master */
|
||
|
|
if (ret) {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
MXC_I2C_SetFrequency(i2c, cfg->bitrate);
|
||
|
|
|
||
|
|
#if defined(CONFIG_I2C_MAX32_INTERRUPT)
|
||
|
|
cfg->irq_config_func(dev);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_I2C_MAX32_INTERRUPT
|
||
|
|
irq_enable(cfg->irqn);
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
data->dev = dev;
|
||
|
|
|
||
|
|
i2c_rtio_init(data->ctx, dev);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct i2c_driver_api max32_driver_api = {
|
||
|
|
.configure = max32_configure,
|
||
|
|
.transfer = max32_transfer,
|
||
|
|
.iodev_submit = max32_submit,
|
||
|
|
};
|
||
|
|
|
||
|
|
#if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
|
||
|
|
#define I2C_MAX32_CONFIG_IRQ_FUNC(n) \
|
||
|
|
.irq_config_func = i2c_max32_irq_config_func_##n, .irqn = DT_INST_IRQN(n),
|
||
|
|
|
||
|
|
#define I2C_MAX32_IRQ_CONFIG_FUNC(n) \
|
||
|
|
static void i2c_max32_irq_config_func_##n(const struct device *dev) \
|
||
|
|
{ \
|
||
|
|
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), i2c_max32_isr, \
|
||
|
|
DEVICE_DT_INST_GET(n), 0); \
|
||
|
|
}
|
||
|
|
#else
|
||
|
|
#define I2C_MAX32_CONFIG_IRQ_FUNC(n)
|
||
|
|
#define I2C_MAX32_IRQ_CONFIG_FUNC(n)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
#define DEFINE_I2C_MAX32(_num) \
|
||
|
|
PINCTRL_DT_INST_DEFINE(_num); \
|
||
|
|
I2C_MAX32_IRQ_CONFIG_FUNC(_num) \
|
||
|
|
static const struct max32_i2c_config max32_i2c_dev_cfg_##_num = { \
|
||
|
|
.regs = (mxc_i2c_regs_t *)DT_INST_REG_ADDR(_num), \
|
||
|
|
.pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
|
||
|
|
.clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
|
||
|
|
.perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
|
||
|
|
.perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \
|
||
|
|
.bitrate = DT_INST_PROP(_num, clock_frequency), \
|
||
|
|
I2C_MAX32_CONFIG_IRQ_FUNC(_num)}; \
|
||
|
|
I2C_RTIO_DEFINE(_i2c##n##_max32_rtio, \
|
||
|
|
DT_INST_PROP_OR(n, sq_size, CONFIG_I2C_RTIO_SQ_SIZE), \
|
||
|
|
DT_INST_PROP_OR(n, cq_size, CONFIG_I2C_RTIO_CQ_SIZE)); \
|
||
|
|
static struct max32_i2c_data max32_i2c_data_##_num = { \
|
||
|
|
.ctx = &CONCAT(_i2c, n, _max32_rtio), \
|
||
|
|
}; \
|
||
|
|
I2C_DEVICE_DT_INST_DEFINE(_num, i2c_max32_init, NULL, &max32_i2c_data_##_num, \
|
||
|
|
&max32_i2c_dev_cfg_##_num, PRE_KERNEL_2, \
|
||
|
|
CONFIG_I2C_INIT_PRIORITY, &max32_driver_api);
|
||
|
|
|
||
|
|
DT_INST_FOREACH_STATUS_OKAY(DEFINE_I2C_MAX32)
|