drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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/*
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* Copyright (c) 2019, Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2020-04-15 13:30:45 +02:00
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#define DT_DRV_COMPAT nordic_qspi_nor
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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#include <errno.h>
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#include <drivers/flash.h>
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#include <init.h>
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#include <string.h>
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#include <logging/log.h>
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#include "spi_nor.h"
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#include "flash_priv.h"
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#include <nrfx_qspi.h>
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#define qspi_nor_config spi_nor_config
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#define QSPI_NOR_MAX_ID_LEN SPI_NOR_MAX_ID_LEN
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/* Status register bits */
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#define QSPI_SECTOR_SIZE SPI_NOR_SECTOR_SIZE
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#define QSPI_BLOCK_SIZE SPI_NOR_BLOCK_SIZE
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/* instance 0 flash size in bytes */
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2020-04-15 13:30:45 +02:00
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#define INST_0_BYTES (DT_INST_PROP(0, size) / 8)
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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2020-04-18 00:21:08 +02:00
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/* for accessing devicetree properties of the bus node */
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#define QSPI_NODE DT_BUS(DT_DRV_INST(0))
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#define QSPI_PROP_AT(prop, idx) DT_PROP_BY_IDX(QSPI_NODE, prop, idx)
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2020-05-28 23:14:20 +02:00
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#define QSPI_PROP_LEN(prop) DT_PROP_LEN(QSPI_NODE, prop)
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2020-04-18 00:21:08 +02:00
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2020-07-20 11:25:25 +02:00
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#define WORD_SIZE 4
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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LOG_MODULE_REGISTER(qspi_nor, CONFIG_FLASH_LOG_LEVEL);
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2020-06-03 20:30:32 +02:00
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static const struct flash_parameters qspi_flash_parameters = {
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2020-06-03 20:33:09 +02:00
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.write_block_size = 1,
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2020-06-03 20:30:32 +02:00
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.erase_value = 0xff,
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};
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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/**
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* @brief QSPI buffer structure
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* Structure used both for TX and RX purposes.
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*
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* @param buf is a valid pointer to a data buffer.
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* Can not be NULL.
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* @param len is the length of the data to be handled.
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* If no data to transmit/receive - pass 0.
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*/
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struct qspi_buf {
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2020-05-27 18:26:57 +02:00
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uint8_t *buf;
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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size_t len;
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};
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/**
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* @brief QSPI command structure
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* Structure used for custom command usage.
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*
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* @param op_code is a command value (i.e 0x9F - get Jedec ID)
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* @param tx_buf structure used for TX purposes. Can be NULL if not used.
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* @param rx_buf structure used for RX purposes. Can be NULL if not used.
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*/
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struct qspi_cmd {
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2020-05-27 18:26:57 +02:00
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uint8_t op_code;
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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const struct qspi_buf *tx_buf;
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const struct qspi_buf *rx_buf;
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};
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/**
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* @brief Structure for defining the QSPI NOR access
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* @param sem The semaphore to access to the flash
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* @param sync The semaphore to ensure that transfer has finished
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* @param write_protection Indicates if write protection for flash
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* device is enabled
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*/
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struct qspi_nor_data {
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struct k_sem sem;
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struct k_sem sync;
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bool write_protection;
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};
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static inline int qspi_get_mode(bool cpol, bool cpha)
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{
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register int ret = -EINVAL;
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if ((!cpol) && (!cpha)) {
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ret = 0;
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} else if (cpol && cpha) {
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ret = 1;
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}
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__ASSERT(ret != -EINVAL, "Invalid QSPI mode");
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return ret;
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}
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static inline bool qspi_is_used_write_quad_mode(nrf_qspi_writeoc_t lines)
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{
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switch (lines) {
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case NRF_QSPI_WRITEOC_PP4IO:
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case NRF_QSPI_WRITEOC_PP4O:
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return true;
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default:
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return false;
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}
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}
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static inline bool qspi_is_used_read_quad_mode(nrf_qspi_readoc_t lines)
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{
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switch (lines) {
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case NRF_QSPI_READOC_READ4IO:
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case NRF_QSPI_READOC_READ4O:
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return true;
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default:
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return false;
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}
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}
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2020-05-27 18:26:57 +02:00
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static inline int qspi_get_lines_write(uint8_t lines)
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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{
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register int ret = -EINVAL;
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switch (lines) {
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case 3:
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ret = NRF_QSPI_WRITEOC_PP4IO;
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break;
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case 2:
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ret = NRF_QSPI_WRITEOC_PP4O;
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break;
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case 1:
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ret = NRF_QSPI_WRITEOC_PP2O;
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break;
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case 0:
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ret = NRF_QSPI_WRITEOC_PP;
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break;
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default:
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break;
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}
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__ASSERT(ret != -EINVAL, "Invalid QSPI write line");
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return ret;
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}
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2020-05-27 18:26:57 +02:00
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static inline int qspi_get_lines_read(uint8_t lines)
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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{
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register int ret = -EINVAL;
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switch (lines) {
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case 4:
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ret = NRF_QSPI_READOC_READ4IO;
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break;
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case 3:
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ret = NRF_QSPI_READOC_READ4O;
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break;
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case 2:
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ret = NRF_QSPI_READOC_READ2IO;
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break;
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case 1:
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ret = NRF_QSPI_READOC_READ2O;
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break;
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case 0:
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ret = NRF_QSPI_READOC_FASTREAD;
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break;
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default:
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break;
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}
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__ASSERT(ret != -EINVAL, "Invalid QSPI read line");
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return ret;
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}
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/**
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* @brief Get QSPI prescaler
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* Get supported frequency prescaler not exceeding the requested one.
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*
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* @param frequency - desired QSPI bus frequency
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* @retval NRF_SPI_PRESCALER in case of success or;
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* -EINVAL in case of failure
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*/
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2020-05-27 18:26:57 +02:00
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static inline nrf_qspi_frequency_t get_nrf_qspi_prescaler(uint32_t frequency)
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
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{
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register int ret = -EINVAL;
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if (frequency < 2000000UL) {
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ret = -EINVAL;
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} else if (frequency >= 32000000UL) {
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ret = NRF_QSPI_FREQ_32MDIV1;
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} else {
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ret = (nrf_qspi_frequency_t)((32000000UL / frequency) - 1);
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}
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__ASSERT(ret != -EINVAL, "Invalid QSPI frequency");
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return ret;
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}
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static inline nrf_qspi_addrmode_t qspi_get_address_size(bool addr_size)
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{
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return addr_size ? NRF_QSPI_ADDRMODE_32BIT : NRF_QSPI_ADDRMODE_24BIT;
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}
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/**
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* @brief Test whether offset is aligned.
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*/
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#define QSPI_IS_SECTOR_ALIGNED(_ofs) (((_ofs) & (QSPI_SECTOR_SIZE - 1U)) == 0)
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#define QSPI_IS_BLOCK_ALIGNED(_ofs) (((_ofs) & (QSPI_BLOCK_SIZE - 1U)) == 0)
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/**
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* @brief Main configuration structure
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*/
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static struct qspi_nor_data qspi_nor_memory_data = {
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.sem = Z_SEM_INITIALIZER(qspi_nor_memory_data.sem, 1, 1),
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.sync = Z_SEM_INITIALIZER(qspi_nor_memory_data.sync, 0, 1),
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};
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/**
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* @brief Converts NRFX return codes to the zephyr ones
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*/
|
2020-04-19 04:25:46 +02:00
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static inline int qspi_get_zephyr_ret_code(nrfx_err_t res)
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
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{
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switch (res) {
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case NRFX_SUCCESS:
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return 0;
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case NRFX_ERROR_INVALID_PARAM:
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case NRFX_ERROR_INVALID_ADDR:
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return -EINVAL;
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|
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case NRFX_ERROR_INVALID_STATE:
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return -ECANCELED;
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case NRFX_ERROR_BUSY:
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case NRFX_ERROR_TIMEOUT:
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default:
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return -EBUSY;
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|
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}
|
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}
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static inline struct qspi_nor_data *get_dev_data(struct device *dev)
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|
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{
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return dev->driver_data;
|
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}
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static inline void qspi_lock(struct device *dev)
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|
|
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{
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struct qspi_nor_data *dev_data = get_dev_data(dev);
|
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k_sem_take(&dev_data->sem, K_FOREVER);
|
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|
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}
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static inline void qspi_unlock(struct device *dev)
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|
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{
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struct qspi_nor_data *dev_data = get_dev_data(dev);
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|
k_sem_give(&dev_data->sem);
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|
|
}
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|
|
|
|
2020-04-19 04:25:46 +02:00
|
|
|
static inline void qspi_wait_for_completion(struct device *dev,
|
|
|
|
nrfx_err_t res)
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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{
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struct qspi_nor_data *dev_data = get_dev_data(dev);
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2020-04-19 04:25:46 +02:00
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if (res == NRFX_SUCCESS) {
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k_sem_take(&dev_data->sync, K_FOREVER);
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}
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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}
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static inline void qspi_complete(struct device *dev)
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{
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struct qspi_nor_data *dev_data = get_dev_data(dev);
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k_sem_give(&dev_data->sync);
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}
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/**
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* @brief QSPI handler
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*
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* @param event Driver event type
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* @param p_context Pointer to context. Use in interrupt handler.
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* @retval None
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*/
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static void qspi_handler(nrfx_qspi_evt_t event, void *p_context)
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{
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struct device *dev = p_context;
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if (event == NRFX_QSPI_EVENT_DONE) {
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qspi_complete(dev);
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}
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}
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/* QSPI send custom command */
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static int qspi_send_cmd(struct device *dev, const struct qspi_cmd *cmd)
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{
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/* Check input parameters */
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if (!cmd) {
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return -EINVAL;
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}
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qspi_lock(dev);
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nrf_qspi_cinstr_conf_t cinstr_cfg = {
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.opcode = cmd->op_code,
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.io2_level = true,
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.io3_level = true,
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.wipwait = false,
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.wren = true,
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};
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cinstr_cfg.length = sizeof(cmd->op_code);
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if ((cmd->tx_buf != 0) && (cmd->rx_buf != 0)) {
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cinstr_cfg.length += cmd->tx_buf->len + cmd->rx_buf->len;
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} else if ((cmd->tx_buf != 0) && (cmd->rx_buf == 0)) {
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cinstr_cfg.length += cmd->tx_buf->len;
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} else if ((cmd->tx_buf == 0) && (cmd->rx_buf != 0)) {
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cinstr_cfg.length += cmd->rx_buf->len;
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}
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int res = nrfx_qspi_cinstr_xfer(&cinstr_cfg, cmd->tx_buf->buf,
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cmd->rx_buf->buf);
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qspi_unlock(dev);
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return qspi_get_zephyr_ret_code(res);
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}
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/* QSPI erase */
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2020-05-27 18:26:57 +02:00
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static int qspi_erase(struct device *dev, uint32_t addr, uint32_t size)
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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{
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2020-05-28 18:15:11 +02:00
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/* address must be sector-aligned */
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if ((addr % QSPI_SECTOR_SIZE) != 0) {
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return -EINVAL;
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}
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/* size must be a non-zero multiple of sectors */
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if ((size == 0) || (size % QSPI_SECTOR_SIZE) != 0) {
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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return -EINVAL;
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}
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2020-05-27 20:13:25 +02:00
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int rv = 0;
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2020-03-09 12:49:07 +01:00
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const struct qspi_nor_config *params = dev->config_info;
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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2020-05-27 20:13:25 +02:00
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qspi_lock(dev);
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while ((rv == 0) && (size > 0)) {
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2020-04-19 04:25:46 +02:00
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nrfx_err_t res = !NRFX_SUCCESS;
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2020-05-27 18:26:57 +02:00
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uint32_t adj = 0;
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2020-04-19 04:25:46 +02:00
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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if (size == params->size) {
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/* chip erase */
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res = nrfx_qspi_chip_erase();
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2020-04-19 04:25:46 +02:00
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adj = size;
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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} else if ((size >= QSPI_BLOCK_SIZE) &&
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QSPI_IS_BLOCK_ALIGNED(addr)) {
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/* 64 kB block erase */
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res = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_64KB, addr);
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2020-04-19 04:25:46 +02:00
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adj = QSPI_BLOCK_SIZE;
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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} else if ((size >= QSPI_SECTOR_SIZE) &&
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QSPI_IS_SECTOR_ALIGNED(addr)) {
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/* 4kB sector erase */
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res = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_4KB, addr);
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2020-04-19 04:25:46 +02:00
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adj = QSPI_SECTOR_SIZE;
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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} else {
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/* minimal erase size is at least a sector size */
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LOG_ERR("unsupported at 0x%lx size %zu", (long)addr, size);
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2020-04-19 04:25:46 +02:00
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rv = -EINVAL;
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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}
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2020-04-19 04:25:46 +02:00
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qspi_wait_for_completion(dev, res);
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if (res == NRFX_SUCCESS) {
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addr += adj;
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size -= adj;
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} else {
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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LOG_ERR("erase error at 0x%lx size %zu", (long)addr, size);
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2020-05-27 20:13:25 +02:00
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rv = qspi_get_zephyr_ret_code(res);
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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}
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}
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2020-05-27 20:13:25 +02:00
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qspi_unlock(dev);
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return rv;
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
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}
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/**
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* @brief Fills init struct
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*
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* @param config Pointer to the config struct provided by user
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* @param initstruct Pointer to the configuration struct
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* @retval None
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*/
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static inline void qspi_fill_init_struct(nrfx_qspi_config_t *initstruct)
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{
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/* Configure XIP offset */
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initstruct->xip_offset = 0;
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/* Configure pins */
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2020-04-18 00:21:08 +02:00
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initstruct->pins.sck_pin = DT_PROP(QSPI_NODE, sck_pin);
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initstruct->pins.csn_pin = QSPI_PROP_AT(csn_pins, 0);
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initstruct->pins.io0_pin = QSPI_PROP_AT(io_pins, 0);
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initstruct->pins.io1_pin = QSPI_PROP_AT(io_pins, 1);
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2020-05-28 23:14:20 +02:00
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#if QSPI_PROP_LEN(io_pins) > 2
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2020-04-18 00:21:08 +02:00
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initstruct->pins.io2_pin = QSPI_PROP_AT(io_pins, 2);
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initstruct->pins.io3_pin = QSPI_PROP_AT(io_pins, 3);
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2020-05-28 23:14:20 +02:00
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#else
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initstruct->pins.io2_pin = NRF_QSPI_PIN_NOT_CONNECTED;
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initstruct->pins.io3_pin = NRF_QSPI_PIN_NOT_CONNECTED;
|
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#endif
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
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|
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/* Configure Protocol interface */
|
2020-04-15 13:30:45 +02:00
|
|
|
#if DT_INST_NODE_HAS_PROP(0, readoc_enum)
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
initstruct->prot_if.readoc =
|
2020-04-15 13:30:45 +02:00
|
|
|
(nrf_qspi_writeoc_t)qspi_get_lines_read(DT_INST_PROP(0, readoc_enum));
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
#else
|
|
|
|
initstruct->prot_if.readoc = NRF_QSPI_READOC_FASTREAD;
|
|
|
|
#endif
|
|
|
|
|
2020-04-15 13:30:45 +02:00
|
|
|
#if DT_INST_NODE_HAS_PROP(0, writeoc_enum)
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
initstruct->prot_if.writeoc =
|
2020-04-15 13:30:45 +02:00
|
|
|
(nrf_qspi_writeoc_t)qspi_get_lines_write(DT_INST_PROP(0, writeoc_enum));
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
#else
|
|
|
|
initstruct->prot_if.writeoc = NRF_QSPI_WRITEOC_PP;
|
|
|
|
#endif
|
|
|
|
initstruct->prot_if.addrmode =
|
2020-04-15 13:30:45 +02:00
|
|
|
qspi_get_address_size(DT_INST_PROP(0, address_size_32));
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
|
|
|
|
initstruct->prot_if.dpmconfig = false;
|
|
|
|
|
|
|
|
/* Configure physical interface */
|
|
|
|
initstruct->phy_if.sck_freq =
|
2020-04-15 13:30:45 +02:00
|
|
|
get_nrf_qspi_prescaler(DT_INST_PROP(0, sck_frequency));
|
|
|
|
initstruct->phy_if.sck_delay = DT_INST_PROP(0, sck_delay);
|
|
|
|
initstruct->phy_if.spi_mode = qspi_get_mode(DT_INST_PROP(0, cpol),
|
|
|
|
DT_INST_PROP(0, cpha));
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
|
|
|
|
initstruct->phy_if.dpmen = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Configures QSPI memory for the transfer */
|
|
|
|
static int qspi_nrfx_configure(struct device *dev)
|
|
|
|
{
|
|
|
|
if (!dev) {
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Main config structure */
|
|
|
|
nrfx_qspi_config_t QSPIconfig;
|
|
|
|
|
|
|
|
qspi_fill_init_struct(&QSPIconfig);
|
|
|
|
|
2020-04-19 04:25:46 +02:00
|
|
|
nrfx_err_t res = nrfx_qspi_init(&QSPIconfig, qspi_handler, dev);
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
|
|
|
|
if (res == NRFX_SUCCESS) {
|
|
|
|
/* If quad transfer was chosen - enable it now */
|
|
|
|
if ((qspi_is_used_write_quad_mode(QSPIconfig.prot_if.writeoc))
|
|
|
|
|| (qspi_is_used_read_quad_mode(QSPIconfig.prot_if.readoc))) {
|
|
|
|
|
|
|
|
/* WRITE ENABLE has to be sent before QUAR ENABLE */
|
|
|
|
struct qspi_cmd cmd = { .op_code = SPI_NOR_CMD_WREN };
|
|
|
|
|
|
|
|
if (qspi_send_cmd(dev, &cmd) != 0) {
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
2020-05-27 18:26:57 +02:00
|
|
|
uint8_t tx = BIT(CONFIG_NORDIC_QSPI_NOR_QE_BIT);
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
|
|
|
|
const struct qspi_buf tx_buff = { .buf = &tx, .len = sizeof(tx), };
|
|
|
|
|
|
|
|
cmd.op_code = SPI_NOR_CMD_WRSR;
|
|
|
|
cmd.tx_buf = &tx_buff;
|
|
|
|
cmd.rx_buf = NULL;
|
|
|
|
|
|
|
|
if (qspi_send_cmd(dev, &cmd) != 0) {
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return qspi_get_zephyr_ret_code(res);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Retrieve the Flash JEDEC ID and compare it with the one expected
|
|
|
|
*
|
|
|
|
* @param dev The device structure
|
|
|
|
* @param flash_id The flash info structure which contains the
|
|
|
|
* expected JEDEC ID
|
|
|
|
* @return 0 on success, negative errno code otherwise
|
|
|
|
*/
|
|
|
|
static inline int qspi_nor_read_id(struct device *dev,
|
|
|
|
const struct qspi_nor_config *const flash_id)
|
|
|
|
{
|
2020-05-27 18:26:57 +02:00
|
|
|
uint8_t rx_b[QSPI_NOR_MAX_ID_LEN];
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
const struct qspi_buf q_rx_buf = {
|
|
|
|
.buf = rx_b,
|
|
|
|
.len = QSPI_NOR_MAX_ID_LEN
|
|
|
|
};
|
|
|
|
const struct qspi_cmd cmd = {
|
|
|
|
.op_code = SPI_NOR_CMD_RDID,
|
|
|
|
.rx_buf = &q_rx_buf,
|
|
|
|
.tx_buf = NULL
|
|
|
|
};
|
|
|
|
|
|
|
|
if (qspi_send_cmd(dev, &cmd) != 0) {
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (memcmp(flash_id->id, rx_b, QSPI_NOR_MAX_ID_LEN) != 0) {
|
|
|
|
LOG_ERR("flash id error. Extected: [%d %d %d], got: [%d %d %d]",
|
|
|
|
flash_id->id[0], flash_id->id[1], flash_id->id[2],
|
|
|
|
rx_b[0], rx_b[1], rx_b[2]);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-07-20 11:25:25 +02:00
|
|
|
static inline nrfx_err_t read_non_aligned(struct device *dev, off_t addr,
|
|
|
|
void *dest, size_t size)
|
|
|
|
{
|
|
|
|
uint8_t __aligned(WORD_SIZE) buf[WORD_SIZE * 2];
|
|
|
|
uint8_t *dptr = dest;
|
|
|
|
|
|
|
|
off_t flash_prefix = (WORD_SIZE - (addr % WORD_SIZE)) % WORD_SIZE;
|
|
|
|
|
|
|
|
if (flash_prefix > size) {
|
|
|
|
flash_prefix = size;
|
|
|
|
}
|
|
|
|
|
|
|
|
off_t dest_prefix = (WORD_SIZE - (off_t)dptr % WORD_SIZE) % WORD_SIZE;
|
|
|
|
|
|
|
|
if (dest_prefix > size) {
|
|
|
|
dest_prefix = size;
|
|
|
|
}
|
|
|
|
|
|
|
|
off_t flash_suffix = (size - flash_prefix) % WORD_SIZE;
|
|
|
|
off_t flash_middle = size - flash_prefix - flash_suffix;
|
|
|
|
off_t dest_middle = size - dest_prefix -
|
|
|
|
(size - dest_prefix) % WORD_SIZE;
|
|
|
|
|
|
|
|
if (flash_middle > dest_middle) {
|
|
|
|
flash_middle = dest_middle;
|
|
|
|
flash_suffix = size - flash_prefix - flash_middle;
|
|
|
|
}
|
|
|
|
|
|
|
|
nrfx_err_t res = NRFX_SUCCESS;
|
|
|
|
|
|
|
|
/* read from aligned flash to aligned memory */
|
|
|
|
if (flash_middle != 0) {
|
|
|
|
res = nrfx_qspi_read(dptr + dest_prefix, flash_middle,
|
|
|
|
addr + flash_prefix);
|
|
|
|
qspi_wait_for_completion(dev, res);
|
|
|
|
if (res != NRFX_SUCCESS) {
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* perform shift in RAM */
|
|
|
|
if (flash_prefix != dest_prefix) {
|
|
|
|
memmove(dptr + flash_prefix, dptr + dest_prefix, flash_middle);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* read prefix */
|
|
|
|
if (flash_prefix != 0) {
|
|
|
|
res = nrfx_qspi_read(buf, WORD_SIZE, addr -
|
|
|
|
(WORD_SIZE - flash_prefix));
|
|
|
|
qspi_wait_for_completion(dev, res);
|
|
|
|
if (res != NRFX_SUCCESS) {
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
memcpy(dptr, buf + WORD_SIZE - flash_prefix, flash_prefix);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* read suffix */
|
|
|
|
if (flash_suffix != 0) {
|
|
|
|
res = nrfx_qspi_read(buf, WORD_SIZE * 2,
|
|
|
|
addr + flash_prefix + flash_middle);
|
|
|
|
qspi_wait_for_completion(dev, res);
|
|
|
|
if (res != NRFX_SUCCESS) {
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
memcpy(dptr + flash_prefix + flash_middle, buf, flash_suffix);
|
|
|
|
}
|
|
|
|
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
static int qspi_nor_read(struct device *dev, off_t addr, void *dest,
|
|
|
|
size_t size)
|
|
|
|
{
|
|
|
|
if (!dest) {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2020-07-20 11:25:25 +02:00
|
|
|
/* read size must be non-zero */
|
|
|
|
if (!size) {
|
|
|
|
return 0;
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
}
|
|
|
|
|
2020-03-09 12:49:07 +01:00
|
|
|
const struct qspi_nor_config *params = dev->config_info;
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
|
2020-05-28 18:15:11 +02:00
|
|
|
/* affected region should be within device */
|
|
|
|
if (addr < 0 ||
|
|
|
|
(addr + size) > params->size) {
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
LOG_ERR("read error: address or size "
|
|
|
|
"exceeds expected values."
|
|
|
|
"Addr: 0x%lx size %zu", (long)addr, size);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
qspi_lock(dev);
|
|
|
|
|
2020-07-20 11:25:25 +02:00
|
|
|
nrfx_err_t res = read_non_aligned(dev, addr, dest, size);
|
2020-04-19 04:25:46 +02:00
|
|
|
|
2020-05-27 20:13:25 +02:00
|
|
|
qspi_unlock(dev);
|
|
|
|
|
2020-05-13 17:49:59 +02:00
|
|
|
int rc = qspi_get_zephyr_ret_code(res);
|
|
|
|
|
|
|
|
return rc;
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
}
|
|
|
|
|
2020-06-04 14:11:25 +02:00
|
|
|
/* addr aligned, sptr not null, slen less than 4 */
|
|
|
|
static inline nrfx_err_t write_sub_word(struct device *dev, off_t addr,
|
|
|
|
const void *sptr, size_t slen)
|
|
|
|
{
|
|
|
|
uint8_t __aligned(4) buf[4];
|
|
|
|
nrfx_err_t res;
|
|
|
|
|
|
|
|
/* read out the whole word so that unchanged data can be
|
|
|
|
* written back
|
|
|
|
*/
|
|
|
|
res = nrfx_qspi_read(buf, sizeof(buf), addr);
|
|
|
|
qspi_wait_for_completion(dev, res);
|
|
|
|
|
|
|
|
if (res == NRFX_SUCCESS) {
|
2020-06-04 19:15:02 +02:00
|
|
|
memcpy(buf, sptr, slen);
|
|
|
|
res = nrfx_qspi_write(buf, sizeof(buf), addr);
|
2020-06-04 14:11:25 +02:00
|
|
|
qspi_wait_for_completion(dev, res);
|
|
|
|
}
|
|
|
|
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2020-06-04 19:15:02 +02:00
|
|
|
BUILD_ASSERT((CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE % 4) == 0,
|
|
|
|
"NOR stack buffer must be multiple of 4 bytes");
|
|
|
|
|
|
|
|
#define NVMC_WRITE_OK (CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE > 0)
|
|
|
|
|
|
|
|
/* If enabled write using a stack-allocated aligned SRAM buffer as
|
|
|
|
* required for DMA transfers by QSPI peripheral.
|
|
|
|
*
|
|
|
|
* If not enabled return the error the peripheral would have produced.
|
|
|
|
*/
|
|
|
|
static inline nrfx_err_t write_from_nvmc(struct device *dev, off_t addr,
|
|
|
|
const void *sptr, size_t slen)
|
|
|
|
{
|
|
|
|
#if NVMC_WRITE_OK
|
|
|
|
uint8_t __aligned(4) buf[CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE];
|
|
|
|
const uint8_t *sp = sptr;
|
|
|
|
nrfx_err_t res = NRFX_SUCCESS;
|
|
|
|
|
|
|
|
while ((slen > 0) && (res == NRFX_SUCCESS)) {
|
|
|
|
size_t len = MIN(slen, sizeof(buf));
|
|
|
|
|
|
|
|
memcpy(buf, sp, len);
|
|
|
|
res = nrfx_qspi_write(buf, sizeof(buf),
|
|
|
|
addr);
|
|
|
|
qspi_wait_for_completion(dev, res);
|
|
|
|
|
|
|
|
if (res == NRFX_SUCCESS) {
|
|
|
|
slen -= len;
|
|
|
|
sp += len;
|
|
|
|
addr += len;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#else /* NVMC_WRITE_OK */
|
|
|
|
nrfx_err_t res = NRFX_ERROR_INVALID_ADDR;
|
|
|
|
#endif /* NVMC_WRITE_OK */
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
static int qspi_nor_write(struct device *dev, off_t addr, const void *src,
|
|
|
|
size_t size)
|
|
|
|
{
|
|
|
|
if (!src) {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2020-06-04 14:11:25 +02:00
|
|
|
/* write size must be non-zero, less than 4, or a multiple of 4 */
|
|
|
|
if ((size == 0)
|
|
|
|
|| ((size > 4) && ((size % 4U) != 0))) {
|
2020-04-19 04:25:46 +02:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
/* address must be 4-byte aligned */
|
|
|
|
if ((addr % 4U) != 0) {
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct qspi_nor_data *const driver_data = dev->driver_data;
|
2020-03-09 12:49:07 +01:00
|
|
|
const struct qspi_nor_config *params = dev->config_info;
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
|
|
|
|
if (driver_data->write_protection) {
|
|
|
|
return -EACCES;
|
|
|
|
}
|
|
|
|
|
2020-05-28 18:15:11 +02:00
|
|
|
/* affected region should be within device */
|
|
|
|
if (addr < 0 ||
|
|
|
|
(addr + size) > params->size) {
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
LOG_ERR("write error: address or size "
|
|
|
|
"exceeds expected values."
|
|
|
|
"Addr: 0x%lx size %zu", (long)addr, size);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2020-06-04 14:11:25 +02:00
|
|
|
nrfx_err_t res = NRFX_SUCCESS;
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
|
2020-06-04 14:11:25 +02:00
|
|
|
qspi_lock(dev);
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
|
2020-06-04 14:11:25 +02:00
|
|
|
if (size < 4U) {
|
|
|
|
res = write_sub_word(dev, addr, src, size);
|
2020-06-04 19:15:02 +02:00
|
|
|
} else if (((uintptr_t)src < CONFIG_SRAM_BASE_ADDRESS)) {
|
|
|
|
res = write_from_nvmc(dev, addr, src, size);
|
2020-06-04 14:11:25 +02:00
|
|
|
} else {
|
|
|
|
res = nrfx_qspi_write(src, size, addr);
|
|
|
|
qspi_wait_for_completion(dev, res);
|
|
|
|
}
|
2020-04-19 04:25:46 +02:00
|
|
|
|
2020-05-27 20:13:25 +02:00
|
|
|
qspi_unlock(dev);
|
|
|
|
|
2020-04-19 04:25:46 +02:00
|
|
|
return qspi_get_zephyr_ret_code(res);
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static int qspi_nor_erase(struct device *dev, off_t addr, size_t size)
|
|
|
|
{
|
|
|
|
struct qspi_nor_data *const driver_data = dev->driver_data;
|
2020-03-09 12:49:07 +01:00
|
|
|
const struct qspi_nor_config *params = dev->config_info;
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
|
|
|
|
if (driver_data->write_protection) {
|
|
|
|
return -EACCES;
|
|
|
|
}
|
|
|
|
|
2020-05-28 18:15:11 +02:00
|
|
|
/* affected region should be within device */
|
|
|
|
if (addr < 0 ||
|
|
|
|
(addr + size) > params->size) {
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
LOG_ERR("erase error: address or size "
|
|
|
|
"exceeds expected values."
|
|
|
|
"Addr: 0x%lx size %zu", (long)addr, size);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
int ret = qspi_erase(dev, addr, size);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int qspi_nor_write_protection_set(struct device *dev,
|
|
|
|
bool write_protect)
|
|
|
|
{
|
|
|
|
struct qspi_nor_data *const driver_data = dev->driver_data;
|
|
|
|
|
|
|
|
int ret = 0;
|
|
|
|
struct qspi_cmd cmd = {
|
|
|
|
.op_code = ((write_protect) ? SPI_NOR_CMD_WRDI : SPI_NOR_CMD_WREN),
|
|
|
|
};
|
|
|
|
|
|
|
|
driver_data->write_protection = write_protect;
|
|
|
|
|
|
|
|
if (qspi_send_cmd(dev, &cmd) != 0) {
|
|
|
|
ret = -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Configure the flash
|
|
|
|
*
|
|
|
|
* @param dev The flash device structure
|
|
|
|
* @param info The flash info structure
|
|
|
|
* @return 0 on success, negative errno code otherwise
|
|
|
|
*/
|
|
|
|
static int qspi_nor_configure(struct device *dev)
|
|
|
|
{
|
2020-03-09 12:49:07 +01:00
|
|
|
const struct qspi_nor_config *params = dev->config_info;
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
|
|
|
|
int ret = qspi_nrfx_configure(dev);
|
|
|
|
|
|
|
|
if (ret != 0) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* now the spi bus is configured, we can verify the flash id */
|
|
|
|
if (qspi_nor_read_id(dev, params) != 0) {
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Initialize and configure the flash
|
|
|
|
*
|
|
|
|
* @param name The flash name
|
|
|
|
* @return 0 on success, negative errno code otherwise
|
|
|
|
*/
|
|
|
|
static int qspi_nor_init(struct device *dev)
|
|
|
|
{
|
2020-04-18 00:21:08 +02:00
|
|
|
IRQ_CONNECT(DT_IRQN(QSPI_NODE), DT_IRQ(QSPI_NODE, priority),
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
nrfx_isr, nrfx_qspi_irq_handler, 0);
|
|
|
|
return qspi_nor_configure(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(CONFIG_FLASH_PAGE_LAYOUT)
|
|
|
|
|
|
|
|
/* instance 0 page count */
|
|
|
|
#define LAYOUT_PAGES_COUNT (INST_0_BYTES / \
|
|
|
|
CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE)
|
|
|
|
|
2020-03-12 16:16:00 +01:00
|
|
|
BUILD_ASSERT((CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE *
|
|
|
|
LAYOUT_PAGES_COUNT)
|
|
|
|
== INST_0_BYTES,
|
|
|
|
"QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE incompatible with flash size");
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
|
|
|
|
static const struct flash_pages_layout dev_layout = {
|
|
|
|
.pages_count = LAYOUT_PAGES_COUNT,
|
|
|
|
.pages_size = CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE,
|
|
|
|
};
|
|
|
|
#undef LAYOUT_PAGES_COUNT
|
|
|
|
|
2020-06-03 20:30:32 +02:00
|
|
|
static const struct flash_parameters *
|
|
|
|
qspi_flash_get_parameters(const struct device *dev)
|
|
|
|
{
|
|
|
|
ARG_UNUSED(dev);
|
|
|
|
|
|
|
|
return &qspi_flash_parameters;
|
|
|
|
}
|
|
|
|
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
static void qspi_nor_pages_layout(struct device *dev,
|
|
|
|
const struct flash_pages_layout **layout,
|
|
|
|
size_t *layout_size)
|
|
|
|
{
|
|
|
|
*layout = &dev_layout;
|
|
|
|
*layout_size = 1;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_FLASH_PAGE_LAYOUT */
|
|
|
|
|
|
|
|
static const struct flash_driver_api qspi_nor_api = {
|
|
|
|
.read = qspi_nor_read,
|
|
|
|
.write = qspi_nor_write,
|
|
|
|
.erase = qspi_nor_erase,
|
|
|
|
.write_protection = qspi_nor_write_protection_set,
|
2020-06-03 20:30:32 +02:00
|
|
|
.get_parameters = qspi_flash_get_parameters,
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
#if defined(CONFIG_FLASH_PAGE_LAYOUT)
|
|
|
|
.page_layout = qspi_nor_pages_layout,
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static const struct qspi_nor_config flash_id = {
|
2020-04-15 13:30:45 +02:00
|
|
|
.id = DT_INST_PROP(0, jedec_id),
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
.size = INST_0_BYTES,
|
|
|
|
};
|
|
|
|
|
2020-04-15 13:30:45 +02:00
|
|
|
DEVICE_AND_API_INIT(qspi_flash_memory, DT_INST_LABEL(0),
|
drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
|
|
|
&qspi_nor_init, &qspi_nor_memory_data,
|
|
|
|
&flash_id, POST_KERNEL, CONFIG_NORDIC_QSPI_NOR_INIT_PRIORITY,
|
|
|
|
&qspi_nor_api);
|