65 lines
1.7 KiB
C
65 lines
1.7 KiB
C
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/*
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* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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#define SAM_PIO_NPINS_PER_BANK 32
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#define SAM_PIO_BANK(pin_id) (pin_id / SAM_PIO_NPINS_PER_BANK)
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#define SAM_PIO_LINE(pin_id) (pin_id % SAM_PIO_NPINS_PER_BANK)
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#define SAM_PIO_BANK_OFFSET 0x40
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#define SAM_GET_PIN_NO(pinmux) ((pinmux) & 0xff)
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#define SAM_GET_PIN_FUNC(pinmux) ((pinmux >> 16) & 0xf)
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#define SAM_GET_PIN_IOSET(pinmux) ((pinmux >> 20) & 0xf)
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static pio_registers_t * const pio_reg =
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(pio_registers_t *)DT_REG_ADDR(DT_NODELABEL(pinctrl));
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static void pinctrl_configure_pin(pinctrl_soc_pin_t pin)
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{
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uint32_t pin_id = SAM_GET_PIN_NO(pin.pin_mux);
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uint32_t bank = SAM_PIO_BANK(pin_id);
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uint32_t line = SAM_PIO_LINE(pin_id);
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uint32_t func = SAM_GET_PIN_FUNC(pin.pin_mux);
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uint32_t conf = 0;
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pio_reg->PIO_GROUP[bank].PIO_MSKR = 1 << line;
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conf = pio_reg->PIO_GROUP[bank].PIO_CFGR;
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if (pin.drive_open_drain) {
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conf |= PIO_CFGR_OPD(PIO_CFGR_OPD_ENABLED_Val);
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}
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if (pin.bias_disable) {
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conf &= ~(PIO_CFGR_PUEN_Msk | PIO_CFGR_PDEN_Msk);
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}
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if (pin.bias_pull_down) {
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conf |= PIO_CFGR_PDEN(PIO_CFGR_PDEN_ENABLED_Val);
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conf &= ~PIO_CFGR_PUEN_Msk;
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}
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if (pin.bias_pull_up) {
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conf |= PIO_CFGR_PUEN(PIO_CFGR_PUEN_ENABLED_Val);
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conf &= ~PIO_CFGR_PDEN_Msk;
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}
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conf &= ~PIO_CFGR_FUNC_Msk;
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conf |= PIO_CFGR_FUNC(func);
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pio_reg->PIO_GROUP[bank].PIO_CFGR = conf;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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ARG_UNUSED(reg);
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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pinctrl_configure_pin(*pins++);
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}
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return 0;
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}
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