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zephyr/drivers/i2s/Kconfig.stm32

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kconfig: Clean up header comments and make them consistent Use this short header style in all Kconfig files: # <description> # <copyright> # <license> ... Also change all <description>s from # Kconfig[.extension] - Foo-related options to just # Foo-related options It's clear enough that it's about Kconfig. The <description> cleanup was done with this command, along with some manual cleanup (big letter at the start, etc.) git ls-files '*Kconfig*' | \ xargs sed -i -E '1 s/#\s*Kconfig[\w.-]*\s*-\s*/# /' Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-11-01 13:45:29 +01:00
# STM32 I2S driver configuration options
drivers: i2s: Add support for I2S stm32 STM32 I2S driver implementation. It has been designed in the most generic way possible, with the possibility of using it in master/slave and rx/tx mode. Currenty it has been tested for master rx mode only using the microphone on ArgonKey board. The configuration file permits to compile it for STM32F4xx product family only, but it should be easy to extend it also for other families. It supports all 5 STM32F4xx I2S controllers (I2S 1/4/5 on APB2 and I2S 2/3 on APB1). It makes uses of the available DMA channels for rx/tx streams. The clock source can be selected among one of the following two choices: - PLLI2S pll, with possibility to configure PLLM/PLLN/PLLR - HSE/HSI clock Interrupt is triggered only in case of errors (FRM/OVR/UDR). Signed-off-by: Armando Visconti <armando.visconti@st.com>
2018-06-14 09:27:46 +02:00
# Copyright (c) 2018 STMicroelectronics
# SPDX-License-Identifier: Apache-2.0
menuconfig I2S_STM32
bool "STM32 MCU I2S controller driver"
drivers: i2s: Update drivers to use devicetree Kconfig symbol Update I2S drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol to expose the driver and enable it by default based on devicetree. We remove 'depend on' Kconfig for symbols that would be implied by the devicetree node existing. Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-24 14:12:33 -05:00
default y
depends on DT_HAS_ST_STM32_I2S_ENABLED
cache: stm32: add new cache API to display and i2s Use sys_cache API to handle cache flush/invalidate. Signed-off-by: Emil Lindqvist <emil@lindq.gr>
2024-01-24 12:42:36 +01:00
select CACHE_MANAGEMENT if CPU_HAS_DCACHE
drivers: i2s: Add support for I2S stm32 STM32 I2S driver implementation. It has been designed in the most generic way possible, with the possibility of using it in master/slave and rx/tx mode. Currenty it has been tested for master rx mode only using the microphone on ArgonKey board. The configuration file permits to compile it for STM32F4xx product family only, but it should be easy to extend it also for other families. It supports all 5 STM32F4xx I2S controllers (I2S 1/4/5 on APB2 and I2S 2/3 on APB1). It makes uses of the available DMA channels for rx/tx streams. The clock source can be selected among one of the following two choices: - PLLI2S pll, with possibility to configure PLLM/PLLN/PLLR - HSE/HSI clock Interrupt is triggered only in case of errors (FRM/OVR/UDR). Signed-off-by: Armando Visconti <armando.visconti@st.com>
2018-06-14 09:27:46 +02:00
select DMA
drivers: stm32: Select PINCTRL when required Select PINCTRL subsystem by drivers which require it. Prevent the need from enabling this symbol at board or soc level. Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2024-08-29 16:04:49 +02:00
select PINCTRL
drivers: i2s: Add support for I2S stm32 STM32 I2S driver implementation. It has been designed in the most generic way possible, with the possibility of using it in master/slave and rx/tx mode. Currenty it has been tested for master rx mode only using the microphone on ArgonKey board. The configuration file permits to compile it for STM32F4xx product family only, but it should be easy to extend it also for other families. It supports all 5 STM32F4xx I2S controllers (I2S 1/4/5 on APB2 and I2S 2/3 on APB1). It makes uses of the available DMA channels for rx/tx streams. The clock source can be selected among one of the following two choices: - PLLI2S pll, with possibility to configure PLLM/PLLN/PLLR - HSE/HSI clock Interrupt is triggered only in case of errors (FRM/OVR/UDR). Signed-off-by: Armando Visconti <armando.visconti@st.com>
2018-06-14 09:27:46 +02:00
help
Enable I2S support on the STM32 family of processors.
i2s: stm32h7: add i2s support for stm32h7 mcu family This commit modifies the I2S driver to work for STM32H7 family of MCU's. Currently only TX is working. Tested on nucleo_stm32h743zi. Requires dma1 & dmamux1 to be enabled. Signed-off-by: Emil Lindqvist <emil@lindq.gr>
2023-11-01 11:54:23 +01:00
(Tested on the STM32F4 & STM32H7 series)
drivers: i2s: Add support for I2S stm32 STM32 I2S driver implementation. It has been designed in the most generic way possible, with the possibility of using it in master/slave and rx/tx mode. Currenty it has been tested for master rx mode only using the microphone on ArgonKey board. The configuration file permits to compile it for STM32F4xx product family only, but it should be easy to extend it also for other families. It supports all 5 STM32F4xx I2S controllers (I2S 1/4/5 on APB2 and I2S 2/3 on APB1). It makes uses of the available DMA channels for rx/tx streams. The clock source can be selected among one of the following two choices: - PLLI2S pll, with possibility to configure PLLM/PLLN/PLLR - HSE/HSI clock Interrupt is triggered only in case of errors (FRM/OVR/UDR). Signed-off-by: Armando Visconti <armando.visconti@st.com>
2018-06-14 09:27:46 +02:00
if I2S_STM32
config I2S_STM32_RX_BLOCK_COUNT
int "RX queue length"
default 4
config I2S_STM32_TX_BLOCK_COUNT
int "TX queue length"
default 4
endif # I2S_STM32
drivers: i2s: add sai support for stm32u5xx This PR adds initial sai support for STM32u5xx Signed-off-by: Mario Paja <mario.paja@zal.aero>
2024-08-06 15:01:25 +02:00
menuconfig I2S_STM32_SAI
bool "STM32 MCU I2S controller driver"
default y
depends on DT_HAS_ST_STM32_SAI_ENABLED
select CACHE_MANAGEMENT if CPU_HAS_DCACHE
select DMA
select USE_STM32_HAL_DMA
select USE_STM32_HAL_DMA_EX
select USE_STM32_HAL_SAI
help
Enable SAI support on the STM32U5 family of processors.
if I2S_STM32_SAI
config I2S_STM32_SAI_BLOCK_COUNT
int "SAI queue length"
default 4
endif # I2S_STM32_SAI
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