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zephyr/drivers/flash/Kconfig.nordic_qspi_nor

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drivers: flash: add Nordic JEDEC QSPI NOR flash driver Most JEDEC NOR flash devices uses not only typical SPI mode (MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS). QSPI mode uses more data lines and as a result provide higher throughput. If this were not enough, Nordic chips provide hardware acceleration for read/write/erase functions, what gives significant performance boost. It does a lot of things "behind the scene", i.e when user has written some data to the flash and would like to read them back, it has to wait until the flash is ready by reading WIP bit in Status Register. This driver does it automatically. Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
# Copyright (c) 2019, Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
menuconfig NORDIC_QSPI_NOR
bool "QSPI NOR Flash"
drivers: flash: Update drivers to use devicetree Kconfig symbol Update flash drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol to expose the driver and enable it by default based on devicetree. We remove 'depend on' Kconfig for symbols that would be implied by the devicetree node existing. Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-22 01:53:16 -05:00
default y
depends on DT_HAS_NORDIC_QSPI_NOR_ENABLED
drivers: flash: add Nordic JEDEC QSPI NOR flash driver Most JEDEC NOR flash devices uses not only typical SPI mode (MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS). QSPI mode uses more data lines and as a result provide higher throughput. If this were not enough, Nordic chips provide hardware acceleration for read/write/erase functions, what gives significant performance boost. It does a lot of things "behind the scene", i.e when user has written some data to the flash and would like to read them back, it has to wait until the flash is ready by reading WIP bit in Status Register. This driver does it automatically. Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
select FLASH_HAS_DRIVER_ENABLED
drivers/flash/nordic_qspi_nor: Add missing FLASH_HAS_PAGE_LAYOUT The Kconfig for device has not been missing the FLASH_HAS_PAGE_LAYOUT. Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
2024-04-12 12:02:24 +00:00
select FLASH_HAS_PAGE_LAYOUT
drivers: nrf_qspi_nor: Mark driver with FLASH_HAS_EXPLICIT_ERASE All QSPI connected NOR Flash devices require erase prior to write. Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
2024-02-08 21:47:11 +00:00
select FLASH_HAS_EXPLICIT_ERASE
drivers: flash: add Nordic JEDEC QSPI NOR flash driver Most JEDEC NOR flash devices uses not only typical SPI mode (MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS). QSPI mode uses more data lines and as a result provide higher throughput. If this were not enough, Nordic chips provide hardware acceleration for read/write/erase functions, what gives significant performance boost. It does a lot of things "behind the scene", i.e when user has written some data to the flash and would like to read them back, it has to wait until the flash is ready by reading WIP bit in Status Register. This driver does it automatically. Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
select NRFX_QSPI
drivers: flash: nrf_qspi: support JESD216 API Refactor slightly so we can read SFDP tables with this driver. Note that the SFDP read command requires long frame mode transfers as data exceeds 8 bytes. Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-12-29 12:11:29 -06:00
select FLASH_JESD216
drivers: nrf: select PINCTRL Drivers for nRF SoCs using pinctrl did not select PINCTRL. This means boards are forced to enable PINCTRL. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-09-19 14:02:22 +02:00
select PINCTRL
drivers: flash: add Nordic JEDEC QSPI NOR flash driver Most JEDEC NOR flash devices uses not only typical SPI mode (MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS). QSPI mode uses more data lines and as a result provide higher throughput. If this were not enough, Nordic chips provide hardware acceleration for read/write/erase functions, what gives significant performance boost. It does a lot of things "behind the scene", i.e when user has written some data to the flash and would like to read them back, it has to wait until the flash is ready by reading WIP bit in Status Register. This driver does it automatically. Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
help
Enable support for nrfx QSPI driver with EasyDMA.
if NORDIC_QSPI_NOR
config NORDIC_QSPI_NOR_INIT_PRIORITY
drivers: flash: nrf_qspi_nor: Add support for XIP at boot Adds support for forcing XIP support at boot time, and reduces the init priority of the driver so that it inits earlier. Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2023-09-08 14:53:45 +01:00
int "Init priority"
default 41
drivers: flash: add Nordic JEDEC QSPI NOR flash driver Most JEDEC NOR flash devices uses not only typical SPI mode (MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS). QSPI mode uses more data lines and as a result provide higher throughput. If this were not enough, Nordic chips provide hardware acceleration for read/write/erase functions, what gives significant performance boost. It does a lot of things "behind the scene", i.e when user has written some data to the flash and would like to read them back, it has to wait until the flash is ready by reading WIP bit in Status Register. This driver does it automatically. Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
help
Device driver initialization priority.
config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE
int "Page size to use for FLASH_LAYOUT feature"
default 65536
help
When CONFIG_FLASH_PAGE_LAYOUT is used this driver will support
that API. By default the page size corresponds to the block
size (65536). Other option include the sector size (4096).
drivers: flash: nrf_qspi_nor: optionally support write from NVMC The Nordic QSPI peripheral uses DMA transfers so data to write must be located in SRAM. Add a Kconfig that enables copying data from NVMC to a stack SRAM buffer so it can be written to flash. Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-06-04 12:15:02 -05:00
config NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE
drivers: flash: nrf_qspi_nor: Fix writing from unaligned RAM buffers Flash API states that drivers should support write requests without any restrictions on location or alignment of the source buffer. Due to hardware limitations of the QSPI peripheral, the nrf_qspi_nor driver currently fails to perform a write from a RAM buffer that is not word-aligned. Fix this by using in such case the same mechanism that is used when the source buffer is located in the internal flash (copy data to a buffer located on stack). Also correct the length parameter for writes from this stack-based buffer to be the actual data chunk length, not always the size of the buffer (as for CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE > 4 this may lead to overwriting of some data located next in the flash). Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-07-13 08:57:48 +02:00
int "Size of a stack-based buffer to handle writes not supported by QSPI"
drivers/flash/nrf_qspi_nor: Default write_from_nvmc buffer size to 4 The commit changes the default size of write_from_nvmc, defined by CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE, to 4, making the write_from_nvmc operation enabled by default. The Kconfig description for the option has been changes more clearly describe how does the option impact compilation. Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
2021-10-05 11:00:50 +00:00
default 4
drivers: flash: nrf_qspi_nor: optionally support write from NVMC The Nordic QSPI peripheral uses DMA transfers so data to write must be located in SRAM. Add a Kconfig that enables copying data from NVMC to a stack SRAM buffer so it can be written to flash. Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-06-04 12:15:02 -05:00
help
drivers: flash: nrf_qspi_nor: Fix writing from unaligned RAM buffers Flash API states that drivers should support write requests without any restrictions on location or alignment of the source buffer. Due to hardware limitations of the QSPI peripheral, the nrf_qspi_nor driver currently fails to perform a write from a RAM buffer that is not word-aligned. Fix this by using in such case the same mechanism that is used when the source buffer is located in the internal flash (copy data to a buffer located on stack). Also correct the length parameter for writes from this stack-based buffer to be the actual data chunk length, not always the size of the buffer (as for CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE > 4 this may lead to overwriting of some data located next in the flash). Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-07-13 08:57:48 +02:00
The QSPI peripheral uses DMA and can only write data that is read
from a word-aligned location in RAM. A non-zero value here enables
a stack buffer to be used for any source data that does not meet
these restrictions. Such data will be copied into this buffer to
allow the write to proceed. Multiple transfers will be initiated
if the data is larger than the configured size.
Must be a multiple of 4. When set to 0, the feature is disabled.
drivers: flash: nrf_qspi_nor: optionally support write from NVMC The Nordic QSPI peripheral uses DMA transfers so data to write must be located in SRAM. Add a Kconfig that enables copying data from NVMC to a stack SRAM buffer so it can be written to flash. Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-06-04 12:15:02 -05:00
drivers: flash: nrf_qspi_nor: Add support for XIP at boot Adds support for forcing XIP support at boot time, and reduces the init priority of the driver so that it inits earlier. Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2023-09-08 14:53:45 +01:00
config NORDIC_QSPI_NOR_XIP
bool "XIP (eXecute in place)"
depends on SOC_NRF5340_CPUAPP
help
Enable setting up the QSPI NOR driver to allow for execution of code
stored in QSPI XIP region. Note that for this functionality to work,
the QSPI NOR init priority must be set so that no XIP code in the
QSPI NOR flash chip is executed until the driver has been setup.
This will also disable power management for the QSPI NOR flash chip.
drivers: qspi: added operation timeout Added Kconfig assignment of qspi timeout. Per nrfx v3.2 addition of qspi timeout in config struct. Signed-off-by: Kelly Helmut Lord <kellyhlord@gmail.com>
2023-12-21 14:00:12 -05:00
config NORDIC_QSPI_NOR_TIMEOUT_MS
int "Timeout for QSPI operations (ms)"
default 500
help
The QSPI peripheral operation timeout in milliseconds.
Primarily intended for long running operations such as
a flash sector erase. The 500 ms default allows for
most typical NOR flash chips to erase a sector.
drivers: flash: add Nordic JEDEC QSPI NOR flash driver Most JEDEC NOR flash devices uses not only typical SPI mode (MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS). QSPI mode uses more data lines and as a result provide higher throughput. If this were not enough, Nordic chips provide hardware acceleration for read/write/erase functions, what gives significant performance boost. It does a lot of things "behind the scene", i.e when user has written some data to the flash and would like to read them back, it has to wait until the flash is ready by reading WIP bit in Status Register. This driver does it automatically. Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
endif # NORDIC_QSPI_NOR
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