zephyr/drivers/clock_control/Kconfig.aspeed

# Copyright (c) 2022 ASPEED Technology Inc.
# SPDX-License-Identifier: Apache-2.0

config CLOCK_CONTROL_AST10X0
	bool "ASPEED clock control driver"
	default y
	depends on DT_HAS_ASPEED_AST10X0_CLOCK_ENABLED
	help
	  This option enables the clock driver for ASPEED AST10X0 series SOC.
drivers: clock_control: add Aspeed AST10x0 clock control AST10x0 series SOCs provide the clock controller through the syscon hardware block. The current driver supports the clock gating capability for the hardware IPs embedded in the SOC. Each clock source has a clock ID that can simply map to a bit in syscon registers CLK_STOP_CTRL0 (group 0) or CLK_STOP_CTRL1 (group 1). There are some clock sources that don't have associated clock gating control, which are always on, are grouped to into group 2. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> 2022-07-22 05:26:28 +02:00			`# Copyright (c) 2022 ASPEED Technology Inc.`
			`# SPDX-License-Identifier: Apache-2.0`

			`config CLOCK_CONTROL_AST10X0`
			`bool "ASPEED clock control driver"`
			`default y`
			`depends on DT_HAS_ASPEED_AST10X0_CLOCK_ENABLED`
			`help`
			`This option enables the clock driver for ASPEED AST10X0 series SOC.`