2019-04-06 15:08:09 +02:00
|
|
|
/* SPDX-License-Identifier: Apache-2.0 */
|
|
|
|
|
2018-10-05 00:02:42 +02:00
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
|
2018-07-31 18:31:44 +02:00
|
|
|
/ {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
compatible = "SiFive,FE310G-0002-Z0-dev", "fe310-dev", "sifive-dev";
|
|
|
|
model = "SiFive,FE310G-0002-Z0";
|
|
|
|
cpus {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2019-07-19 05:07:45 +02:00
|
|
|
cpu: cpu@0 {
|
2018-07-31 18:31:44 +02:00
|
|
|
clock-frequency = <0>;
|
|
|
|
compatible = "sifive,rocket0", "riscv";
|
|
|
|
device_type = "cpu";
|
|
|
|
i-cache-block-size = <64>;
|
|
|
|
i-cache-sets = <128>;
|
|
|
|
i-cache-size = <16384>;
|
|
|
|
next-level-cache = <&modeselect &maskrom &otp &spi0>;
|
|
|
|
reg = <0>;
|
|
|
|
riscv,isa = "rv32imac";
|
|
|
|
sifive,dtim = <&dtim>;
|
|
|
|
sifive,itim = <&itim>;
|
|
|
|
status = "okay";
|
|
|
|
timebase-frequency = <32768>;
|
|
|
|
hlic: interrupt-controller {
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
compatible = "riscv,cpu-intc";
|
|
|
|
interrupt-controller;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
soc {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
compatible = "SiFive,FE310G-0002-Z0-soc", "fe310-soc",
|
|
|
|
"sifive-soc", "simple-bus";
|
|
|
|
ranges;
|
|
|
|
aon: aon@10000000 {
|
|
|
|
compatible = "sifive,aon0";
|
|
|
|
interrupt-parent = <&plic>;
|
|
|
|
interrupts = <1 2>;
|
|
|
|
reg = <0x10000000 0x1000>;
|
|
|
|
reg-names = "control";
|
|
|
|
};
|
|
|
|
clint: clint@2000000 {
|
|
|
|
compatible = "riscv,clint0";
|
|
|
|
interrupts-extended = <&hlic 3 &hlic 7>;
|
|
|
|
reg = <0x2000000 0x10000>;
|
|
|
|
reg-names = "control";
|
|
|
|
};
|
|
|
|
debug: debug-controller@0 {
|
|
|
|
compatible = "sifive,debug-013", "riscv,debug-013";
|
|
|
|
interrupts-extended = <&hlic 65535>;
|
|
|
|
reg = <0x0 0x1000>;
|
|
|
|
reg-names = "control";
|
|
|
|
};
|
|
|
|
dtim: dtim@80000000 {
|
|
|
|
compatible = "sifive,dtim0";
|
|
|
|
reg = <0x80000000 0x4000>;
|
|
|
|
reg-names = "mem";
|
|
|
|
};
|
|
|
|
error-device@3000 {
|
|
|
|
compatible = "sifive,error0";
|
|
|
|
reg = <0x3000 0x1000>;
|
|
|
|
reg-names = "mem";
|
|
|
|
};
|
|
|
|
gpio0: gpio@10012000 {
|
|
|
|
compatible = "sifive,gpio0";
|
2018-10-05 00:02:42 +02:00
|
|
|
gpio-controller;
|
2018-07-31 18:31:44 +02:00
|
|
|
interrupt-parent = <&plic>;
|
|
|
|
interrupts = <8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
|
|
|
|
26 27 28 29 30 31 32 33 34 35 36 37 38 39>;
|
|
|
|
reg = <0x10012000 0x1000>;
|
|
|
|
reg-names = "control";
|
2019-03-20 23:58:07 +01:00
|
|
|
label = "gpio_0";
|
2018-07-31 18:31:44 +02:00
|
|
|
status = "disabled";
|
2018-10-05 00:02:42 +02:00
|
|
|
#gpio-cells = <2>;
|
2018-07-31 18:31:44 +02:00
|
|
|
};
|
|
|
|
i2c0: i2c@10016000 {
|
|
|
|
compatible = "sifive,i2c0";
|
|
|
|
interrupt-parent = <&plic>;
|
|
|
|
interrupts = <52>;
|
|
|
|
reg = <0x10016000 0x1000>;
|
|
|
|
reg-names = "control";
|
2018-11-29 01:45:40 +01:00
|
|
|
label = "i2c_0";
|
2018-07-31 18:31:44 +02:00
|
|
|
status = "disabled";
|
2019-06-19 07:20:17 +02:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2018-07-31 18:31:44 +02:00
|
|
|
};
|
|
|
|
plic: interrupt-controller@c000000 {
|
|
|
|
#interrupt-cells = <1>;
|
dts: riscv: Add sifive,plic-1.0.0 binding and fix riscv,ndev values
Add a new sifive,plic-1.0.0 binding that inherits from the riscv,plic0
binding. The new binding adds a required riscv,ndev property, which
gives the number of external interrupts supported.
Use the new binding for microsemi-miv.dtsi (with a value of 31 for
riscv,ndev, from http://www.actel.com/ipdocs/MiV_RV32IMAF_L1_AHB_HB.pdf)
and riscv32-fe310.dtsi (which already assigns riscv,ndev).
Also remove a spurious riscv,ndev assignment from
riscv32-litex-vexriscv.dtsi.
Also make edtlib and the old scripts/dts/ scripts replace '.' in
compatible strings with '_' when generating identifiers.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-08-01 18:14:52 +02:00
|
|
|
compatible = "sifive,plic-1.0.0";
|
2018-07-31 18:31:44 +02:00
|
|
|
interrupt-controller;
|
|
|
|
interrupts-extended = <&hlic 11>;
|
2020-03-24 00:34:46 +01:00
|
|
|
reg = <0x0c000000 0x00002000
|
|
|
|
0x0c002000 0x001fe000
|
|
|
|
0x0c200000 0x03e00000>;
|
2018-12-01 00:17:03 +01:00
|
|
|
reg-names = "prio", "irq_en", "reg";
|
2018-07-31 18:31:44 +02:00
|
|
|
riscv,max-priority = <7>;
|
|
|
|
riscv,ndev = <52>;
|
|
|
|
};
|
|
|
|
itim: itim@8000000 {
|
|
|
|
compatible = "sifive,itim0";
|
|
|
|
reg = <0x8000000 0x4000>;
|
|
|
|
reg-names = "mem";
|
|
|
|
};
|
|
|
|
otp: otp@10010000 {
|
|
|
|
compatible = "sifive,otp0";
|
|
|
|
reg = <0x10010000 0x1000 0x20000 0x2000>;
|
|
|
|
reg-names = "control", "mem";
|
|
|
|
};
|
|
|
|
prci: prci@10008000 {
|
|
|
|
compatible = "sifive,freedome300prci0";
|
|
|
|
reg = <0x10008000 0x1000>;
|
|
|
|
reg-names = "control";
|
|
|
|
};
|
|
|
|
pwm0: pwm@10015000 {
|
|
|
|
compatible = "sifive,pwm0";
|
|
|
|
interrupt-parent = <&plic>;
|
|
|
|
interrupts = <40 41 42 43>;
|
|
|
|
reg = <0x10015000 0x1000>;
|
|
|
|
reg-names = "control";
|
2018-11-21 23:20:21 +01:00
|
|
|
label = "pwm_0";
|
2018-07-31 18:31:44 +02:00
|
|
|
status = "disabled";
|
2018-11-21 23:20:21 +01:00
|
|
|
sifive,compare-width = <8>;
|
2018-11-01 21:20:05 +01:00
|
|
|
#pwm-cells = <2>;
|
2018-07-31 18:31:44 +02:00
|
|
|
};
|
|
|
|
pwm1: pwm@10025000 {
|
|
|
|
compatible = "sifive,pwm0";
|
|
|
|
interrupt-parent = <&plic>;
|
|
|
|
interrupts = <44 45 46 47>;
|
|
|
|
reg = <0x10025000 0x1000>;
|
|
|
|
reg-names = "control";
|
2018-11-21 23:20:21 +01:00
|
|
|
label = "pwm_1";
|
2018-07-31 18:31:44 +02:00
|
|
|
status = "disabled";
|
2018-11-21 23:20:21 +01:00
|
|
|
sifive,compare-width = <16>;
|
2018-11-01 21:20:05 +01:00
|
|
|
#pwm-cells = <2>;
|
2018-07-31 18:31:44 +02:00
|
|
|
};
|
|
|
|
pwm2: pwm@10035000 {
|
|
|
|
compatible = "sifive,pwm0";
|
|
|
|
interrupt-parent = <&plic>;
|
|
|
|
interrupts = <48 49 50 51>;
|
|
|
|
reg = <0x10035000 0x1000>;
|
|
|
|
reg-names = "control";
|
2018-11-21 23:20:21 +01:00
|
|
|
label = "pwm_2";
|
2018-07-31 18:31:44 +02:00
|
|
|
status = "disabled";
|
2018-11-21 23:20:21 +01:00
|
|
|
sifive,compare-width = <16>;
|
2018-11-01 21:20:05 +01:00
|
|
|
#pwm-cells = <2>;
|
2018-07-31 18:31:44 +02:00
|
|
|
};
|
|
|
|
modeselect: rom@1000 {
|
|
|
|
compatible = "sifive,modeselect0";
|
|
|
|
reg = <0x1000 0x1000>;
|
|
|
|
reg-names = "mem";
|
|
|
|
};
|
|
|
|
maskrom: rom@10000 {
|
|
|
|
compatible = "sifive,maskrom0";
|
|
|
|
reg = <0x10000 0x2000>;
|
|
|
|
reg-names = "mem";
|
|
|
|
};
|
|
|
|
uart0: serial@10013000 {
|
|
|
|
compatible = "sifive,uart0";
|
|
|
|
interrupt-parent = <&plic>;
|
|
|
|
interrupts = <3>;
|
|
|
|
reg = <0x10013000 0x1000>;
|
|
|
|
reg-names = "control";
|
|
|
|
label = "uart_0";
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
uart1: serial@10023000 {
|
|
|
|
compatible = "sifive,uart0";
|
|
|
|
interrupt-parent = <&plic>;
|
|
|
|
interrupts = <4>;
|
|
|
|
reg = <0x10023000 0x1000>;
|
|
|
|
reg-names = "control";
|
2019-04-24 14:34:32 +02:00
|
|
|
label = "uart_1";
|
2018-07-31 18:31:44 +02:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
spi0: spi@10014000 {
|
|
|
|
compatible = "sifive,spi0";
|
|
|
|
interrupt-parent = <&plic>;
|
|
|
|
interrupts = <5>;
|
|
|
|
reg = <0x10014000 0x1000 0x20000000 0x20000000>;
|
|
|
|
reg-names = "control", "mem";
|
2018-11-21 20:30:29 +01:00
|
|
|
label = "spi_0";
|
2018-07-31 18:31:44 +02:00
|
|
|
status = "disabled";
|
2019-06-19 07:20:17 +02:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2018-07-31 18:31:44 +02:00
|
|
|
};
|
|
|
|
spi1: spi@10024000 {
|
|
|
|
compatible = "sifive,spi0";
|
|
|
|
interrupt-parent = <&plic>;
|
|
|
|
interrupts = <6>;
|
|
|
|
reg = <0x10024000 0x1000>;
|
|
|
|
reg-names = "control";
|
2018-11-21 20:30:29 +01:00
|
|
|
label = "spi_1";
|
2018-07-31 18:31:44 +02:00
|
|
|
status = "disabled";
|
2019-06-19 07:20:17 +02:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2018-07-31 18:31:44 +02:00
|
|
|
};
|
|
|
|
spi2: spi@10034000 {
|
|
|
|
compatible = "sifive,spi0";
|
|
|
|
interrupt-parent = <&plic>;
|
|
|
|
interrupts = <7>;
|
|
|
|
reg = <0x10034000 0x1000>;
|
|
|
|
reg-names = "control";
|
2018-11-21 20:30:29 +01:00
|
|
|
label = "spi_2";
|
2018-07-31 18:31:44 +02:00
|
|
|
status = "disabled";
|
2019-06-19 07:20:17 +02:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2018-07-31 18:31:44 +02:00
|
|
|
};
|
|
|
|
teststatus: teststatus@4000 {
|
|
|
|
compatible = "sifive,test0";
|
|
|
|
reg = <0x4000 0x1000>;
|
|
|
|
reg-names = "control";
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|