2017-01-24 12:52:21 +01:00
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/*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the ARM Ltd MPS2.
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*
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*/
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#ifndef _ARM_MPS2_REGS_H_
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#define _ARM_MPS2_REGS_H_
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2022-05-06 11:11:04 +02:00
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#include <zephyr/sys/util.h>
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Introduce new sized integer typedefs
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t. This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.
We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.
We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.
Jira: ZEP-2051
Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-19 17:32:08 +02:00
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#include <zephyr/types.h>
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2017-01-24 12:52:21 +01:00
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2017-01-06 14:59:03 +01:00
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/* Registers in the FPGA system control block */
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struct mps2_fpgaio {
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/* Offset: 0x000 LED connections */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t led0;
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2017-01-06 14:59:03 +01:00
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/* Offset: 0x004 RESERVED */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t reserved1;
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2017-01-06 14:59:03 +01:00
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/* Offset: 0x008 Buttons */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t button;
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2017-01-06 14:59:03 +01:00
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/* Offset: 0x00c RESERVED */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t reserved2;
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2017-01-06 14:59:03 +01:00
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/* Offset: 0x010 1Hz up counter */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t clk1hz;
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2017-01-06 14:59:03 +01:00
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/* Offset: 0x014 100Hz up counter */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t clk100hz;
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2017-01-06 14:59:03 +01:00
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/* Offset: 0x018 Cycle up counter */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t counter;
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2017-01-06 14:59:03 +01:00
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/* Offset: 0x01c Reload value for prescale counter */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t prescale;
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2017-01-06 14:59:03 +01:00
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/* Offset: 0x020 32-bit Prescale counter */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t pscntr;
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2017-01-06 14:59:03 +01:00
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/* Offset: 0x024 RESERVED */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t reserved3[10];
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2017-01-06 14:59:03 +01:00
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/* Offset: 0x04c Misc control */
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2020-05-27 18:26:57 +02:00
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volatile uint32_t misc;
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2017-01-06 14:59:03 +01:00
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};
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/* Defines for bits in fpgaio led0 register */
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#define FPGAIO_LED0_USERLED0 0
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#define FPGAIO_LED0_USERLED1 1
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/* Defines for bits in fpgaio button register */
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#define FPGAIO_BUTTON_USERPB0 0
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#define FPGAIO_BUTTON_USERPB1 1
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/* Defines for bits in fpgaio misc register */
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#define FPGAIO_MISC_CLCD_CS 0
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#define FPGAIO_MISC_SPI_SS 1
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#define FPGAIO_MISC_CLCD_RESET 3
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#define FPGAIO_MISC_CLCD_RS 4
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#define FPGAIO_MISC_CLCD_RD 5
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#define FPGAIO_MISC_CLCD_BL_CTRL 6
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#define FPGAIO_MISC_ADC_SPI_CS 7
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#define FPGAIO_MISC_SHIELD0_SPI_CS 8
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#define FPGAIO_MISC_SHIELD1_SPI_CS 9
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2017-01-24 12:52:21 +01:00
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#endif /* _ARM_MPS2_REGS_H_ */
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