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zephyr/dts/bindings/interrupt-controller/cypress,psoc6-intmux-ch.yaml

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soc: arm: cypress: psoc6: Add Cortex-M0+ int mux support PSoC-6 SoC needs that user define the nvic interrupt number to bind with the peripheral interrupt line for the Cortex-M0+ CPU. It uses a multiplex before any NVIC interrupt line. The interrupt vector is selected using interrupt-parent property with the intmux_chN number reference. Note: The PSoC-6 SoC allows that both CPUs receive the same interrupt. A tipical use is GPIO interrupt handle and user is responsable to define interrupt line, priority and take care of enable same peripheral instance on both CPUs only when appropriated. Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2020-09-25 23:38:32 +02:00
# Copyright (c) 2019, Linaro Limited
# Copyright (c) 2020, ATL Electronics
# SPDX-License-Identifier: Apache-2.0
description: |
Cypress Interrupt Multiplex Channel
see cypress,psoc6-intmux
compatible: "cypress,psoc6-intmux-ch"
include: [interrupt-controller.yaml, base.yaml]
properties:
reg:
yamllint: indentation: fix dts/bindings/ Fix the YAML files indentation for files in dts/bindings/. Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-01-03 20:21:25 +01:00
required: true
soc: arm: cypress: psoc6: Add Cortex-M0+ int mux support PSoC-6 SoC needs that user define the nvic interrupt number to bind with the peripheral interrupt line for the Cortex-M0+ CPU. It uses a multiplex before any NVIC interrupt line. The interrupt vector is selected using interrupt-parent property with the intmux_chN number reference. Note: The PSoC-6 SoC allows that both CPUs receive the same interrupt. A tipical use is GPIO interrupt handle and user is responsable to define interrupt line, priority and take care of enable same peripheral instance on both CPUs only when appropriated. Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2020-09-25 23:38:32 +02:00
interrupts:
yamllint: indentation: fix dts/bindings/ Fix the YAML files indentation for files in dts/bindings/. Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-01-03 20:21:25 +01:00
required: true
soc: arm: cypress: psoc6: Add Cortex-M0+ int mux support PSoC-6 SoC needs that user define the nvic interrupt number to bind with the peripheral interrupt line for the Cortex-M0+ CPU. It uses a multiplex before any NVIC interrupt line. The interrupt vector is selected using interrupt-parent property with the intmux_chN number reference. Note: The PSoC-6 SoC allows that both CPUs receive the same interrupt. A tipical use is GPIO interrupt handle and user is responsable to define interrupt line, priority and take care of enable same peripheral instance on both CPUs only when appropriated. Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
2020-09-25 23:38:32 +02:00
interrupt-cells:
- irq
- priority
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