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zephyr/arch/xtensa/core/cpu_idle.c

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Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-22 17:21:34 +01:00
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
xtensa: set no optimization for arch_cpu_idle() with xt-clang xt-clang likes to remove any consecutive NOPs more than 8. So we need to force the function to have no optimization to avoid this behavior and to retain all those NOPs. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-07-19 22:36:27 +02:00
#include <zephyr/toolchain.h>
arch: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all arch code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 10:49:15 +02:00
#include <zephyr/tracing/tracing.h>
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-22 17:21:34 +01:00
arch/xtensa: clean up arch_cpu_idle function Some workarounds were introduced for intel cavs2.5 platform bring up. It is not general so move them to platform code. Signed-off-by: Rander Wang <rander.wang@intel.com>
2023-11-03 06:53:54 +01:00
#ifndef CONFIG_ARCH_CPU_IDLE_CUSTOM
kernel: rename z_arch_ to arch_ Promote the private z_arch_* namespace, which specifies the interface between the core kernel and the architecture code, to a new top-level namespace named arch_*. This allows our documentation generation to create online documentation for this set of interfaces, and this set of interfaces is worth treating in a more formal way anyway. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-11-07 21:43:29 +01:00
void arch_cpu_idle(void)
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-22 17:21:34 +01:00
{
debug: tracing: Remove unneeded abstraction Various C and Assembly modules make function calls to z_sys_trace_*. These merely call corresponding functions sys_trace_*. This commit is to simplify these by making direct function calls to the sys_trace_* functions from these modules. Subsequently, the z_sys_trace_* functions are removed. Signed-off-by: Mrinal Sen <msen@oticon.com>
2019-09-19 09:25:19 +02:00
sys_trace_idle();
xtensa: use inline assembly instead of XT_* macros XT_* macros are defined in xtensa HAL headers as xcc intrinsics. gcc does not have any of these intrinsics. Replace XT_* macros with inline assembly or provide gcc-compatible definitions. Change-Id: If823ea8a7898a11a3a8363b17efdba27dee4c6a4 Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-02-15 23:57:29 +01:00
__asm__ volatile ("waiti 0");
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-22 17:21:34 +01:00
}
arch/xtensa: clean up arch_cpu_idle function Some workarounds were introduced for intel cavs2.5 platform bring up. It is not general so move them to platform code. Signed-off-by: Rander Wang <rander.wang@intel.com>
2023-11-03 06:53:54 +01:00
#endif
arch/xtensa: Add arch_cpu_idle() workarounds A simple WAITI isn't sufficient in all cases. The cAVS 2.5 hardware uses WAITI as the entry state for per-core power gating, which is very difficult to debug. Provide a fallback that simply spins in the idle loop waiting for interrupts to provide a stable system while this feature stabilizes. Also, the SOF code for those platforms references a known bug with the Xtensa LX6 core IP (or at least some versions), and will prefix the WAIT instruction with 128 NOP.N's followed by an ISYNC and EXTW. This bug hasn't been seen under Zephyr yet, and details are sketchy. But the code is simply enough to import and works correctly. Place both workaround under new kconfig variables and select them both (even though they're actually mutually exclusive -- if you select both CPU_IDLE_SPIN overrides) for cavs_v25. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-08-13 18:29:31 +02:00
kernel: rename z_arch_ to arch_ Promote the private z_arch_* namespace, which specifies the interface between the core kernel and the architecture code, to a new top-level namespace named arch_*. This allows our documentation generation to create online documentation for this set of interfaces, and this set of interfaces is worth treating in a more formal way anyway. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-11-07 21:43:29 +01:00
void arch_cpu_atomic_idle(unsigned int key)
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-22 17:21:34 +01:00
{
debug: tracing: Remove unneeded abstraction Various C and Assembly modules make function calls to z_sys_trace_*. These merely call corresponding functions sys_trace_*. This commit is to simplify these by making direct function calls to the sys_trace_* functions from these modules. Subsequently, the z_sys_trace_* functions are removed. Signed-off-by: Mrinal Sen <msen@oticon.com>
2019-09-19 09:25:19 +02:00
sys_trace_idle();
xtensa: use inline assembly instead of XT_* macros XT_* macros are defined in xtensa HAL headers as xcc intrinsics. gcc does not have any of these intrinsics. Replace XT_* macros with inline assembly or provide gcc-compatible definitions. Change-Id: If823ea8a7898a11a3a8363b17efdba27dee4c6a4 Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-02-15 23:57:29 +01:00
__asm__ volatile ("waiti 0\n\t"
"wsr.ps %0\n\t"
"rsync" :: "a"(key));
Xtensa port: Added Xtensa specific code (C + S) files. Change-Id: I0dff0c33d8577cc70d4d5ee8f298db38c508ee73 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-22 17:21:34 +01:00
}
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