8 lines
524 B
Markdown
8 lines
524 B
Markdown
|
---
|
||
|
|
title: "Toy 8 bit CPU"
|
||
|
|
date: 2024-01-21
|
||
|
|
---
|
||
|
|
I decided to step back from the full 6502 and implement a toy 8 bit processor.
|
||
|
|
|
||
|
|
I ended up implementing Soo-Ik Chae's architecture from https://ocw.snu.ac.kr/sites/default/files/NOTE/6639.pdf. Zachary Yedidia's [SystemVerilog Guide](https://zyedidia.github.io/notes/sv_guide.pdf) was a useful guide to idiomatic SystemVerilog, and David Money Harris's MIPS implementation from [CMOS VLSI Design 4th Ed.](https://pages.hmc.edu/harris/cmosvlsi/4e/index.html) was very readable.
|