98 lines
1.8 KiB
Markdown
98 lines
1.8 KiB
Markdown
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---
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title: "Learning FPGAs #1"
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date: 2024-01-01
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---
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I normally work at the system or electronic level, and one thing I've always wanted to learn is FPGAs and the corresponding HDLs.
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To pull this together, I plan to implement the 6502 using Verilog on an OrangeCrab board. The board uses a ECP5-25F and is supported by Yosys.
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## 6502
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I chose the 6502 as it reminds me of the VIC-20 and C128 I used to own, and it has
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a small, straight forward instruction set.
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According to https://llx.com/Neil/a2/opcodes.html, most instructions have a `aaabbbcc` format, where `aaa` and `cc` determine the opcode and `bbb` is the addressing mode. https://www.pagetable.com/c64ref/6502/ has a nice 3-3-2 view of this.
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The instructions are divided into groups based on `cc`:
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- 00 is group 3
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- 01 is group 1
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- 10 is group 2
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- 11 is reserved
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## Group 1 (c = 01)
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Covers 1/4th of the decode space, where `aaa` is:
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- 000 ORA
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- 001 AND
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- 010 EOR
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- 011 ADC
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- 100 STA
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- 101 LDA
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- 110 CMP
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- 111 SBC
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and `bbb` is:
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- 000 (zero page,X)
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- 001 zero page
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- 010 #immediate
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- 011 absolute
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- 100 (zero page),Y
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- 101 zero page,X
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- 110 absolute,Y
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- 111 absolute,X
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## Group 2 (c = 10)
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- 000 ASL
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- 001 ROL
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- 010 LSR
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- 011 ROR
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- 100 STX
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- 101 LDX
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- 110 DEC
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- 111 INC
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where `bbb` is:
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- 000 #immediate
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- 001 zero page
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- 010 accumulator
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- 011 absolute
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- 101 zero page,X
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- 111 absolute,X
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So zero page, absolute, zero page, X, and absolute, X are the same.
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## Group 3 (c = 00)
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- 001 BIT
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- 010 JMP
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- 011 JMP (abs)
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- 100 STY
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- 101 LDY
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- 110 CPY
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- 111 CPX
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where `bbb` is:
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- 000 #immediate
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- 001 zero page
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- 011 absolute
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- 101 zero page,X
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- 111 absolute,X
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which is the same as group 2 except `accumulator`.
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The conditional branches have the form `xxy 100 00`, i.e. b is 100 and c is 00, and x is:
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- 00 negative
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- 01 overflow
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- 10 carry
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- 11 zero
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which is compared with `y`.
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Next is to implement the ALU.
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