121 lines
4.2 KiB
C++
121 lines
4.2 KiB
C++
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2012 LeafLabs, LLC.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file wirish/stm32f2/boards_setup.cpp
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* @author Marti Bolivar <mbolivar@leaflabs.com>
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* @brief STM32F2 chip setup.
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*
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* This file controls how init() behaves on the STM32F2. Be very
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* careful when changing anything here. Many of these values depend
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* upon each other.
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*/
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#include "boards_private.h"
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#include <libmaple/gpio.h>
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#include <libmaple/syscfg.h>
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#include <libmaple/libmaple_types.h>
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#include <wirish/wirish_types.h>
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#include <board/board.h>
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// PLL config for 25 MHz external crystal --> 120 MHz SYSCLK, with
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// 48 MHz PLL48CK.
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#ifndef BOARD_PLL_Q
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#define BOARD_PLL_Q 5
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#endif
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#ifndef BOARD_PLL_P
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#define BOARD_PLL_P 2
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#endif
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#ifndef BOARD_PLL_N
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#define BOARD_PLL_N 240
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#endif
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#ifndef BOARD_PLL_M
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#define BOARD_PLL_M 25
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#endif
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static stm32f2_rcc_pll_data pll_data = {BOARD_PLL_Q,
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BOARD_PLL_P,
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BOARD_PLL_N,
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BOARD_PLL_M};
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namespace wirish {
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namespace priv {
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// PLL clocked off of HSE, with above configuration data.
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
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// Global ADC prescaler
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//
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// On F2, with f_APB2 = 60 MHz, we need f_ADC = f_PCLK2 / 2 to
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// get the (maximum) f_ADC = 30 MHz.
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__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_2;
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// Conservative ADC sample rate. Goal is error less than 1/4
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// LSB with 50 KOhm input impedance.
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//
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// On F2, with f_ADC = 30 MHz, error is acceptable assuming an
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// internal sample and hold capacitance C_ADC at most 8.8 pF
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// (ST doesn't specify the maximum C_ADC, so we had to take a
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// guess). See Equation 1 and Table 61 in the F2 datasheet for
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// more details.
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__weak adc_smp_rate w_adc_smp = ADC_SMPR_144;
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__weak void board_reset_pll(void) {
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// Set PLLCFGR to its reset value.
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RCC_BASE->PLLCFGR = 0x24003010; // FIXME lose the magic number.
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}
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__weak void board_setup_clock_prescalers(void) {
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// On F2, with f_SYSCLK = 120 MHz (as determined by
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// board_pll_cfg),
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//
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// f_AHB = f_SYSCLK / 1 = 120 MHz
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// f_APB1 = f_AHB / 4 = 30 MHz
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// f_APB2 = f_AHB / 2 = 60 MHz
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rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1);
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rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_4);
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rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_2);
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}
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__weak void board_setup_gpio(void) {
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gpio_init_all();
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}
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__weak void board_setup_usb(void) {
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// Nothing to do.
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}
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__weak void series_init(void) {
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// We need SYSCFG for external interrupts
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syscfg_init();
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// Turn on the I/O compensation cell, since we drive the
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// GPIOs quickly by default.
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syscfg_enable_io_compensation();
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}
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}
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}
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