65 lines
2.2 KiB
Plaintext
65 lines
2.2 KiB
Plaintext
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FSMC notes (for maple native and other "high density" STM32 devices)
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-------------------------------------------------------------------------------
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There is an application note for all this which is helpful; see the ST website.
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SRAM chip details
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IS62WV51216BLL
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512k x 16
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19 address input
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16 data inputs
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t_wc (write cycle) = 55ns
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t_rc (write cycle) = 55ns
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t_pwe1 (write enable low pulse) = 40ns
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t_aa (address access) = 55ns
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The FSMC nomenclature is very confusing. There are three separate
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"banks" (which I will call "peripheral banks") each specialized for
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different types of external memory (NOR flash, NAND flash, SRAM,
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etc). We use the one for "PSRAM" with our SRAM chip; it's bank #1. The
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SRAM peripheral bank is further split into 4 "banks" (which I will
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call "channels") to support multiple external devices with chip select
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pins. I think what's going on is that there are 4 hardware peripherals
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and many sections of RAM; the docs are confusing about what's a "block
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of memeory" and what's an "FSMC block".
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Anyways, this all takes place on the AHB memory bus.
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I'm going to use not-extended mode 1 for read/write.
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Steps from application note:
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- enable bank3: BCR3_MBKEN = '1'
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- memory type is SRAM: BCR3_MTYP = '00'
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- databuse weidth is 16bits: BCR3_MWID = '01'
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- memory is nonmultiplexed: BCR3_MEXEN is reset (= '0')
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- everything else is cleared
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But not true! Actually write enable needs to be set.
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Using the application note, which is based around a very similar chip (with
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faster timing), I calculated an ADDSET (address setup) value of 0x0 and a
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DATAST (data setup) value of 0x3.
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Using channel1, NOR/PSRAM1 memory starts at 0x60000000.
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Have to turn on the RCC clock for all those GPIO pins, but don't need to use
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any interrupts.
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Not-super-helpful-link:
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http://www.keil.com/support/man/docs/mcbstm32e/mcbstm32e_to_xmemory.htm
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Note the possible confusion with address spaces, bitwidths, rollovers, etc.
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TODO
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-------------------------------------------------------------------------------
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- more rigorous testing: throughput, latency, bounds checking, bitwidth, data
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resiliance, etc.
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- update .ld scripts to transparently make use of this external memory
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- test/demo using a seperate external SRAM chip or screen
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- write up documentation
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