29518f6e34
The current versions of DELARE_*_TIMER() don't play well with cscope, which is a bad sign. Fix that. Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>
236 lines
9.7 KiB
C
236 lines
9.7 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2011, 2012 LeafLabs, LLC.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/timer_private.h
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* @author Marti Bolivar <mbolivar@leaflabs.com>
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* @brief Private, internal timer APIs.
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*/
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#ifndef _LIBMAPLE_TIMER_PRIVATE_H_
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#define _LIBMAPLE_TIMER_PRIVATE_H_
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/*
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* Helper macros for declaring timer_devs of various timer_types
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*/
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/* The indexes of user handlers in a timer_dev.handlers are just like
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* the corresponding DIER bits, as follows: */
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/* Advanced timers:
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* [0] = Update handler;
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* [1,2,3,4] = capture/compare 1,2,3,4 handlers, respectively;
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* [5] = COM;
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* [6] = TRG;
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* [7] = BRK. */
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#define NR_ADV_HANDLERS 8
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/* General purpose timers:
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* [0] = update;
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* [1,2,3,4] = capture/compare 1,2,3,4;
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* [5] = <junk>;
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* [6] = trigger. */
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#define NR_GEN_HANDLERS 7
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/* Basic timers:
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* [0] = update. */
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#define NR_BAS_HANDLERS 1
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/* For declaring advanced timers. */
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#define ADVANCED_TIMER(num) \
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{ \
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.regs = { .adv = TIMER##num##_BASE }, \
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.clk_id = RCC_TIMER##num, \
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.type = TIMER_ADVANCED, \
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.handlers = { [NR_ADV_HANDLERS - 1] = 0 }, \
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}
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/* For declaring full-featured general purpose timers. */
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#define GENERAL_TIMER(num) \
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{ \
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.regs = { .gen = TIMER##num##_BASE }, \
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.clk_id = RCC_TIMER##num, \
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.type = TIMER_GENERAL, \
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.handlers = { [NR_GEN_HANDLERS - 1] = 0 }, \
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}
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/* For declaring general purpose timers with limited interrupt
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* capability (e.g. timers 9 through 14 on STM32F2 and XL-density
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* STM32F1). */
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#define RESTRICTED_GENERAL_TIMER(num, max_dier_bit) \
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{ \
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.regs = { .gen = TIMER##num##_BASE }, \
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.clk_id = RCC_TIMER##num, \
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.type = TIMER_GENERAL, \
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.handlers = { [max_dier_bit] = 0 }, \
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}
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/* For declaring basic timers (e.g. TIM6 and TIM7). */
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#define BASIC_TIMER(num) \
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{ \
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.regs = { .bas = TIMER##num##_BASE }, \
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.clk_id = RCC_TIMER##num, \
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.type = TIMER_BASIC, \
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.handlers = { [NR_BAS_HANDLERS - 1] = 0 }, \
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}
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/*
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* IRQ handlers
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*
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* These decode TIMx_DIER and TIMx_SR, then dispatch to the user-level
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* IRQ handlers. They also clean up TIMx_SR afterwards, so the user
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* doesn't have to deal with register details.
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*
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* Notes:
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*
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* - These dispatch routines make use of the fact that DIER interrupt
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* enable bits and SR interrupt flags have common bit positions.
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* Thus, ANDing DIER and SR lets us check if an interrupt is enabled
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* and if it has occurred simultaneously.
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*
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* - We force these routines to inline to avoid call overhead, but
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* there aren't any measurements to prove that this is actually a
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* good idea. Profile-directed optimizations are definitely wanted. */
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/* A special-case dispatch routine for timers which only serve a
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* single interrupt on a given IRQ line.
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*
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* This function still checks DIER & SR, as in some cases, a timer may
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* only serve a single interrupt on a particular NVIC line, but that
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* line may be shared with another timer. For example, the timer 1
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* update interrupt shares an IRQ line with the timer 10 interrupt on
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* STM32F1 (XL-density), STM32F2, and STM32F4. */
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static __always_inline void dispatch_single_irq(timer_dev *dev,
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timer_interrupt_id iid,
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uint32 irq_mask) {
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timer_bas_reg_map *regs = (dev->regs).bas;
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if (regs->DIER & regs->SR & irq_mask) {
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void (*handler)(void) = dev->handlers[iid];
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if (handler) {
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handler();
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regs->SR &= ~irq_mask;
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}
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}
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}
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/* Helper macro for dispatch routines which service multiple interrupts. */
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#define handle_irq(dier_sr, irq_mask, handlers, iid, handled_irq) do { \
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if ((dier_sr) & (irq_mask)) { \
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void (*__handler)(void) = (handlers)[iid]; \
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if (__handler) { \
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__handler(); \
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handled_irq |= (irq_mask); \
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} \
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} \
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} while (0)
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static __always_inline void dispatch_adv_brk(timer_dev *dev) {
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dispatch_single_irq(dev, TIMER_BREAK_INTERRUPT, TIMER_SR_BIF);
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}
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static __always_inline void dispatch_adv_up(timer_dev *dev) {
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dispatch_single_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF);
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}
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static __always_inline void dispatch_adv_trg_com(timer_dev *dev) {
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timer_adv_reg_map *regs = (dev->regs).adv;
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uint32 dsr = regs->DIER & regs->SR;
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void (**hs)(void) = dev->handlers;
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uint32 handled = 0; /* Logical OR of SR interrupt flags we end up
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* handling. We clear these. User handlers
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* must clear overcapture flags, to avoid
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* wasting time in output mode. */
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handle_irq(dsr, TIMER_SR_TIF, hs, TIMER_TRG_INTERRUPT, handled);
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handle_irq(dsr, TIMER_SR_COMIF, hs, TIMER_COM_INTERRUPT, handled);
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regs->SR &= ~handled;
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}
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static __always_inline void dispatch_adv_cc(timer_dev *dev) {
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timer_adv_reg_map *regs = (dev->regs).adv;
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uint32 dsr = regs->DIER & regs->SR;
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void (**hs)(void) = dev->handlers;
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uint32 handled = 0;
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handle_irq(dsr, TIMER_SR_CC4IF, hs, TIMER_CC4_INTERRUPT, handled);
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handle_irq(dsr, TIMER_SR_CC3IF, hs, TIMER_CC3_INTERRUPT, handled);
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handle_irq(dsr, TIMER_SR_CC2IF, hs, TIMER_CC2_INTERRUPT, handled);
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handle_irq(dsr, TIMER_SR_CC1IF, hs, TIMER_CC1_INTERRUPT, handled);
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regs->SR &= ~handled;
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}
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static __always_inline void dispatch_general(timer_dev *dev) {
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timer_gen_reg_map *regs = (dev->regs).gen;
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uint32 dsr = regs->DIER & regs->SR;
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void (**hs)(void) = dev->handlers;
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uint32 handled = 0;
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handle_irq(dsr, TIMER_SR_TIF, hs, TIMER_TRG_INTERRUPT, handled);
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handle_irq(dsr, TIMER_SR_CC4IF, hs, TIMER_CC4_INTERRUPT, handled);
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handle_irq(dsr, TIMER_SR_CC3IF, hs, TIMER_CC3_INTERRUPT, handled);
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handle_irq(dsr, TIMER_SR_CC2IF, hs, TIMER_CC2_INTERRUPT, handled);
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handle_irq(dsr, TIMER_SR_CC1IF, hs, TIMER_CC1_INTERRUPT, handled);
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handle_irq(dsr, TIMER_SR_UIF, hs, TIMER_UPDATE_INTERRUPT, handled);
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regs->SR &= ~handled;
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}
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/* On F1 (XL-density), F2, and F4, TIM9 and TIM12 are restricted
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* general-purpose timers with update, CC1, CC2, and TRG interrupts. */
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static __always_inline void dispatch_tim_9_12(timer_dev *dev) {
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timer_gen_reg_map *regs = (dev->regs).gen;
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uint32 dsr = regs->DIER & regs->SR;
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void (**hs)(void) = dev->handlers;
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uint32 handled = 0;
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handle_irq(dsr, TIMER_SR_TIF, hs, TIMER_TRG_INTERRUPT, handled);
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handle_irq(dsr, TIMER_SR_CC2IF, hs, TIMER_CC2_INTERRUPT, handled);
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handle_irq(dsr, TIMER_SR_CC1IF, hs, TIMER_CC1_INTERRUPT, handled);
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handle_irq(dsr, TIMER_SR_UIF, hs, TIMER_UPDATE_INTERRUPT, handled);
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regs->SR &= ~handled;
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}
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/* On F1 (XL-density), F2, and F4, timers 10, 11, 13, and 14 are
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* restricted general-purpose timers with update and CC1 interrupts. */
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static __always_inline void dispatch_tim_10_11_13_14(timer_dev *dev) {
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timer_gen_reg_map *regs = (dev->regs).gen;
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uint32 dsr = regs->DIER & regs->SR;
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void (**hs)(void) = dev->handlers;
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uint32 handled = 0;
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handle_irq(dsr, TIMER_SR_CC1IF, hs, TIMER_CC1_INTERRUPT, handled);
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handle_irq(dsr, TIMER_SR_UIF, hs, TIMER_UPDATE_INTERRUPT, handled);
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regs->SR &= ~handled;
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}
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static __always_inline void dispatch_basic(timer_dev *dev) {
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dispatch_single_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF);
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}
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#endif
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